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Day - 23 - Latch Up
Day - 23 - Latch Up
What is Latch-up?
• Latch-up is a condition that can occur in a circuit fabricated
in a bulk CMOS technology. When a chip is in a state of latch –
up it draws a large current from the power supply but does
not function in response to input stimuli. A chip may be
operating normally and then enter a state of latch-up; in this
case , removing and reconnecting the power supply may
restore operations.
In other words
•Latch-up is the creation of a low impedance path between
the power supply rails.
• Latch-up is caused by the triggering of parasitic bipolar
structures within an integrated circuit when applying a
current or voltage stimulus on an input, output, or I/O pin
or by an over-voltage on the power supply pin.
Temporary versus true latch-up:
•Fab/Design Approaches
1. Reduce the gain product b1 x b1
• move n-well and n+ source/drain farther apart increases width of
the base of Q2 and reduces gain beta2 > also reduces circuit
density
• buried n+ layer in well reduces gain of Q1
2. Reduce the well and substrate resistances, producing lower voltage
drops
• higher substrate doping level reduces Rsub
• reduce Rwell by making low resistance contact to GND
• guard rings around p- and/or n-well, with frequent contacts to the
rings, reduces the parasitic resistances.
Latch-up on CMOS
Inherent in bulk CMOS processes are parasitic bipolar
transistors forming p+/n /p /n+ path between VDD and VSS