System Control

The System Control Block includes several system features and

control registers for a number of functions that are not related to
specific peripheral devices. These include:
Crystal Oscillator
 External Interrupt Inputs
 Miscellaneous System Controls and Status
 Memory Mapping Control
 PLL
 Power Control
 Reset
 APB Divider
 Wakeup Timer
 Oscillator

XTAL1
XTAL2
an input signal of 50-50 duty cycle within a
frequency range from 1 MHz to 50 MHz can be used
by the LPC2141/2/4/6/8 if supplied to its input XTAL1
pin
Microcontroller’s onboard oscillator circuit supports
external crystals in the range of 1 MHz
to 30 MHz only.
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If the on-chip PLL system is used, the input clock

frequency is limited to an exclusive range of 10 MHz
to 25 MHz
The oscillator output frequency is called FOSC and
the ARM processor clock frequency is referred to as
CCLK
Fosc=CCLK if the PLL is not running
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In slave mode the input clock signal should be

coupled by means of a capacitor of 100 pF

The X2 pin in this configuration can be left not

connected.

If slave mode is selected, the FOSC signal of 50-50

duty cycle can range from 1 MHz to 50 MHz.
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Choosing an oscillation mode as an on-board

oscillator mode of operation limits FOSC clock
selection to 1 MHz to 30 MHz.
 Phase Locked Loop (PLL)

There are two PLL modules in the LPC2141/2/4/6/8

microcontroller.
The PLL0 is used to generate the CCLK clock
(system clock) while the PLL1 has to supply the
clock for the USB at the fixed rate of 48 MHz.
Structurally these two PLLs are identical with
exception of the PLL interrupt capabilities reserved
only for the PLL0.
Basic PLL Configuration

Ref. -https://www.analog.com/en/analog-dialogue/articles/phase-locked-loop-
pll-fundamentals.html#
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The PLL0 and PLL1 accept an input clock frequency

in the range of 10 MHz to 25 MHz only.

The input frequency is multiplied up the range of 10

MHz to 60 MHz for the CCLK and 48 MHz for the
USB clock using a Current Controlled Oscillators
(CCO).
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The multiplier can be an integer value from 1 to 32

The CCO operates in the range of 156 MHz to 320
MHz
There is an additional divider in the loop to keep the
CCO within its frequency range while the PLL is
providing the desired output frequency.
The output divider may be set to divide by 1, 2, 4, or
8 to produce the output clock.
 PLL Frequency Calculation

Fosc: the frequency from the crystal

oscillator/external oscillator
Fcco: The frequency of the PLL current controlled
oscillator
CCLK: The PLL output frequency (also the
processor clock frequency)
M: PLL Multiplier value
P: PLL Divider value
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CCLK = M * Fosc
The Fcco frequency can be computed as:
Fcco = CCLK * 2 * P
or
Fcco = Fosc * M * 2 * P
Fosc range :10 MHz to 25 MHz
CCLK : 10 MHz to 60 MHz
Fcco : 150 MHz to 320 MHz
 PLL Configuration

The PLL is enabled by software only.

The program must configure and activate the PLL,

wait for the PLL to Lock, then connect to the PLL as
a clock source.

Registers are used to configure the PLL

PLL0CON PLL0 Control Register. Holding 0xE01F C080
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register for updating PLL control
bits. Values written to this
register do not take effect until a
valid PLL feed sequence has
taken place.
PLL1CON PLL1 Control Register. 0xE01F C0A0

PLL0CFG PLL0 Configuration Register 0xE01F C084

PLL1CFG PLL1 Configuration Register 0xE01F C0A4
PLL0STAT PLL0 Status Register. 0xE01F C088
PLL1STAT PLL1 Status Register 0xE01F C0A8
PLL0FEED PLL0 Feed Register. This register 0xE01F C08C
enables loading of the PLL control
and configuration information from
the PLLCON and PLLCFG registers
into the shadow registers that
actually affect PLL operation.

PLL1FEED PLL1 Feed Register 0xE01F C0AC

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PLL Control register (PLL0CON - 0xE01F C080, PLL1CON

-0xE01F C0A0)
Bit Symbol Description
0 PLLE PLL Enable
1 PLLC PLL Connect
2:7 Reserved

0 0 --- Turned off

0 1 --- PLL is active but not yet connected
1 0 --- PLL is not enabled
1 1 --- PLL is enabled and Connected
PLL Configuration register (PLL0CFG - 0xE01F
C084, PLL1CFG -0xE01F C0A4)

4:0 MSEL PLL Multiplier value. Supplies the value

"M" in the PLL frequency calculation

6:5 PSEL PLL Divider value. Supplies the value "P"

in the PLL frequency calculations.
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PLL Feed register (PLL0FEED - 0xE01F C08C,

PLL1FEED -0xE01F C0AC)
correct feed sequence must be written to the
PLLFEED register in order for changes to the
PLLCON and PLLCFG registers to take effect. The
feed sequence is:
1. Write the value 0xAA to PLLFEED.
2. Write the value 0x55 to PLLFEED
Bits(6:5) P Bits(4:0) M
00 1 00000 1
01 2 00001 2
10 4 00010 3
11 8 00011 4
11110 31
11111 32
Example:
Fosc= 10 MHz
Required CCLK = 60 MHz
Determine value of P and M
Pmin = 150/(2*CCLK) = 1.3
Pmax = 350/(2*CCLK) = 2.7
P=2
M=60/10 = 6
The data to be loaded into PLLxCFG (x: 0 or 1)
Since P = 2
Bits (6:5) = 01
M=6
Bits (4:0) = 00101
Bit 7 : Reserved
PLL0CFG = 00100101b
 Procedure for determining PLL settings

Choose the desired processor operating frequency

(CCLK). This may be based on processor throughput
requirements, need to support a specific set of
UART baud rates, etc.

Choose an oscillator frequency (FOSC). CCLK must

be the whole (non-fractional) multiple of FOSC.

Find the value of P and M

 Programming Exercise

Write a Program to generate 60 MHz CCLK if

Fosc=10 MHz