This poster describes the design architecture for Distributed Arithmetic for FIR filter and comparison results when compared to traditional FIR filters.
This poster describes the design architecture for Distributed Arithmetic for FIR filter and comparison results when compared to traditional FIR filters.
This poster describes the design architecture for Distributed Arithmetic for FIR filter and comparison results when compared to traditional FIR filters.
Vidyaya Amrutham Applications. Ashnuthe Challa Bhavya, Esha S, Gayathri S, Dr. Yasha Jyothi M Shirur, Department of ECE, B.N.M. Institute of Technology, Bengaluru
Abstract DA Based Implementation of FIR filter
FIR filters are used in many performance/power critical applications such as mobile communication devices, analogue to digital converters and digital signal processing applications. In designing FIR filters, Multiply-Accumulate (MAC) unit is used. MAC comprises of multiplier, adder and an accumulator. Faster adder and multiplier circuits are required for high speed MAC unit. But MAC based structures have disadvantages like high power dissipation, slow processing etc. The multiplication operation where input data is to be multiplied with the fixed coefficients considerably took large place to store their temporary data. So, memory based multiplication technique substitute multipliers to reduce area and latency of system. Distributed Arithmetic (DA) is one of the memory based technique. In DA based FIR filter architecture the partial products of the FIR filter coefficients are pre-calculated and stored in LUTs. The filtering operation Results is done by shift-accumulation unit.
FIR Filter structure
MAC based FIR Filter
Conclusions & Applications
The major highlights of the DA based architecture for FIR filters are: The conventional Finite Impulse Response filters use multipliers, adders and delay elements to produce the required output. The multipliers which multiplies input with the fixed content Distributed Arithmetic architecture significantly occupies more place to store their temporary values and also increases the power consumption .So, these multipliers are replaced with memory based structures to reduce area and power. The above technique holds good only when we go for lower order filters. For higher order filters, the size of the LUT also increases exponentially with the order of the filter. Reduces the area requirement by 27.9% and power requirement by 12.64%, making it suitable for low power and low area consumption applications.