PROJECT GUIDE PRESENTED BY

Dr.N.UMAPATHI G.LAVANYA
H.NO.18271D5704
Title Advantage Disadvantage
An area efficient reduction in area and drastically degrades in
interpolation filter for power consumption terms of area
digital audio applications
Title Advantage Disadvantage
Design of high-speed Digital Signal Processing not possible at the cost of
carry saves adder using (DSP) applications some tradeoff between
carry look ahead Adder which includes Fast area & power.
Fourier Transform
(FFT), Digital filters,
multipliers.
Title Advantage Disadvantage

A power consumption Reduction of number of Unable to deal with

and area improved design multiplications power consumption
of IIR decimation filters
via MDT
Title Advantage Disadvantage
A Reduced-sp-D3Lsum reduce the propagation low dynamic power
Adder-Based High delay
Frequency
4 × 4 Bit Multiplier
Using Dadda Algorithm
Title Advantage Disadvantage
Low power CMOS pass Power estimation and equivalent architecture
logic 4-2 compressor for speed are to be level approaches with
high-speed examined. zero hardware
multiplication
Title Advantage Disadvantage
An area efficient efficient in terms of both performance drastically
interpolation filter for area and power degrades in terms of area
digital audio consumption.
applications
Title Advantage Disadvantage
Novel ultra low-voltage low power dissipation leakage current
and high-speed CMOS and superior variability
pass transistor logic together with low
transistor count
Title Advantage Disadvantage
Digital Circuit comparable with a gate scaling problem
Optimization via geometric program or
Geometric generalized geometric
Programming, program
Operations Research
Title Advantage Disadvantage

Low-power Full Adder

array-based Multiplier lower power dissipation Critical Path
with Domino Logic
Title Advantage Disadvantage
Low power and high- reduction in power problem with bypassed
speed multiplier design consumption
with row bypassing and
parallel architecture
Title Advantage Disadvantage
An area efficient interpolation reduction in area and power drastically degrades in terms of
filter for digital audio consumption area
applications
Design of high-speed carry Digital Signal Processing (DSP) not possible at the cost of some
saves adder using carry look applications which includes Fast tradeoff between area & power.
ahead Adder Fourier Transform (FFT), Digital
filters, multipliers.
A power consumption and area Reduction of number of Unable to deal with power
improved design of IIR multiplications consumption
decimation filters via MDT
A Reduced-sp-D3Lsum Adder- reduce the propagation delay low dynamic power
Based High Frequency
4 × 4 Bit Multiplier Using
Dadda Algorithm
Low power CMOS pass logic 4- Power estimation and speed are equivalent architecture level
2 compressor for high-speed to be examined. approaches with zero hardware
multiplication
Title
An area efficient interpolation
filter for digital audio
applications
Novel ultra low-voltage and
high-speed CMOS pass
transistor logic
Digital Circuit Optimization via
Geometric Programming,
Operations Research
Low-power Full Adder array-
based Multiplier with Domino
Logic
Low power and high-speed
multiplier design
with row bypassing and parallel
architecture
Advantage Disadvantage
efficient in terms of both area performance drastically
and power consumption. degrades in terms of area
low power dissipation and leakage current
superior variability together with
low transistor count
comparable with a geometric gate scaling problem
program or generalized
geometric program
lower power dissipation
Critical Path
reduction in power consumption problem with bypassed
Step 1 : 16 partial products are generated using AND gate.
Step 2 : The height of the tree is reduced using Dadda stage
using one-half adder (HA) and three full adders (FA).
Step 3 : The reduction is done by two half adders and two full
adders.
Step 4 : Used a ripple carry adder.
Finally, results are passed through the buffer to make the
output
THANK YOU