By

B.RAVINA
17HM1D5701

Under the guidance of

Mr. P.ANJANEYA M.Tech(Ph.d).,
Dept. of E.C.E
 The main objective of this work is to reduce the
Power and Area in Dadda Multiplier using OFA.
 As the technology growing day by day and due to the
necessity of portable, fast and low power devices.
VLSI technology facing a challenging role in acquiring
the above parameters with an accurate trade off.
 Multipliers are the basic building blocks of an ALU, so
it is very prominent to design the multipliers efficiently
in such a manner which gives low power and high
packing density .
 Again in multipliers adders are the basic building
blocks so if we design the adders with low power and
area then the design of multiplier becomes effective.
 Dadda Multiplier is a hardware multiplier design
similar to wallace multiplier.
 Unlike Wallace multipliers that perform reduction as
much as possible on each layer, Dadda multipliers do
as reduction as possible.
 Dadda multiplier implies that fewer columns are
compressed in the initial stages of the column
compression tree, and more columns in the later levels
of the multiplier.
 Dadda Multiplier consists of partial products ,HA,FA.
Number of stages in Dadda multiplier
A = Multiplicand
B = Multiplier

Partial products

Product
1 0 0 1 0 1 0
0 0 0 0 0
1 0 0
0

1 0 0 1 0 1 0
0 0 0 0 0
0 1 0 0

0 0 0 1 0 1 0
1 0 1 0 0 0

0 1 0 1 1 0 1 0
 Dadda Multiplier is designed using conventional
full adder which has more area and high power
consumption due to its basic building block which is
FA.
Number of transistors are more in conventional FA.
High power.
 In proposed system, Dadda multiplier using
OFA is designed, to reduce the power and area when
compared to the conventional design.
A full adder is a major block in the multiplier. Full
adder has been modified in order to produce low power
consumption and less area by reducing the number of
transistors in its design.
Adders Area (No. of Power
Transistors)
Conventional FA 42 5.385mW

Proposed OFA 12 0.138mW

4-bit
Multiplier Area(No. of Power
Transistors)
Multiplier using FA 400 1167.081mW

Multiplier using OFA 160 824.779mW

8-bit
Multiplier Area (No. of Power
Transistors)
Multiplier using 2144 4844.245mW
FA
Multiplier using 704 676.786mW
OFA
Dsch v2
Microwind v3.1
 Dadda multiplier is designed by considering low
power adder in the transistor level which is referred as
OFA, with the results obtained the proposed multiplier
is compared with the conventional one and concluded
that the proposed design gives low power.
Parameter Array Wallace Tree Dadda
Multiplier

Delay Very high Medium Less

Area Minimum Medium Medium

Power(Conven More More More

tional FA)

Power(OFA) Less More Medium

 [1] Zain Shabbir, Anas Razzaq Ghumman, Shabbir Majeed
Chaudhry, A Reduced-sp-D3Lsum Adder-Based High Frequency
4 × 4 Bit Multiplier Using Dadda Algorithm, Springer
Science+Business Media New York 2015.

 [2]V. Kayathri, C. Kumar, P. Mari Muthu, N. Naveen Kumar,

POWER REDUCTION IN FULL ADDER USING NEW
HYBRID LOGIC, International Journal of Current Research and
Modern Education (IJCRME)2016,(Coimbatore, Tamilnadu).

 [3] Y. Berg, M. Azadmehr,"Novel ultra low-voltage and high-

speed CMOS pass transistor logic", Proceedings of the IEEE,
Faible Tension Faible Consommation (FTFC), Paris, 2012.