GEETHANJALI INSTITUTE OF SCIENCE AND TECHNOLOGY:

NELLORE

Department of Electronics and Communication Engineering

Design and Implemention of FIR Filter With Vedic Multiplier and

Modified HSCG-SCG SQRT CSLA Adder

Project by
SD. Reshma - 182U1A04G0
SK. Saleeha - 182U1A04E2
S.Pooja - 182U1A04F2
K. Sireesha -172U1A04E7

Under Guidance by

Mr. U. Penchalaiah, Associate

Professor/ECE
 Abstract
IN DIGITAL SIGNAL PROCESSING FIR FILTERS ARE PLAYING VERY IMPORTANT ROLE. IN THIS WORK, FIR FILTER

HAS BEEN DESIGNED USING A VEDIC MULTIPLIER WITH MODIFIED SQRT-CSLA (CARRY SELECT ADDER).

THE COMBINATION OF THE VEDIC MULTIPLIER AND MODIFIED SQRT-CSLA (CARRY SELECT ADDER) MAKES THE

FIR FILTER IS BETTER THAN EXISTING FILTER .

IN ORDER TO IMPROVE THE PERFORMANCE OF WE NEED TO IMPROVE THE BASIC BUILDING BLOCKS

PERFORMANCE.

THIS CAN NOT DONE DIRECTLY SO WE NEED TO FOCUS ON INTERNAL BLOCKS FIR FILTER LIKE ADDERS AND

MULTIPLIERS IN TERMS OF REDUCING THE AREA , POWER AND DELAY .

FINALLY THIS CAN DESIGN 8,16,32 AND 64 BITS AND COMPARE WITH EXISTING FILTER AND PROVED THAT

PROSED FILTER IS HIGHSPEED FILTER.

 Introduction
 In recent years of technology development in Signal processing application an FIR (Finite impulse response)

plays an important role in designing an efficient digital signal processing system.

 The filter design will have a highly compactable with high performance and low power in all digital signal

processing application, such as audio, signal processing, software defined radio and many more.

 FIR filter is a type of digital filter, which is used for linear characteristics applications.

 Various types of techniques have been proposed for the designing of the FIR filter.

 In this we used modified SQRT CSLA adders with Vedic multipliers .

 The selected multiplier and adder should be faster.

 Existing Mechanism

 The SQRT Carry select adder has required large area , power and delay, so to improve the performance of

adder we propose the new adder.

 The existing FIR filter consumes the large area , power and delay.

 In SQRT-CSLA half sum generations are not temporarily generated so that we are going for proposed

mechanism.
 Drawbacks
 High power consumptions.

 larger area.

 Low performance.
 Proposed mechanism
 The proposed design we are replacing the existing SQRT CSLA adder by HSCG-SCG adder.
 The proposed adder with vedic multiplier are implement in FIR filter.
 The proposed FIR filter design with HSCG-SCG adder and Vedic multiplier upto 64 bits and
compare with existing filter in terms for area,power and delay.
 The HSCG-SCG has internal block.They are Half sum generation,Full sum Generation,Full
Carry Generation,Half Carry Generation.
 These design will reduction of number of logic gate’s will have compared to existing Design.
Block Diagram
FIR Filter
 Preferred technology
 Software- Xilinux 14.2 –ISE
 Programming Language- VHDL
 Advantages
 Low power consumptions.

 Less area.

 High performance.
 Applications

 Low Pass Filter

 High Pass Filter
 In all DSP Applications
 References
 Y.Bharat Kumar,Dr.V.G.Siva Kumar,performance Analysis of FIR Filter Design Using Vedic
Multiplier With SQRT based Carry Select Adder
 Basant Kumar Mohanty, Senior Member, IEEE, and Pramod Kumar Meher, Senior Member, "A
High-Performance FIR Filter Architecture for Fixed and Reconfigurable Applications", 1063-
8210 © 2015 IEEE.
 U Penchalaiah, Siva Kumar VG, “Performance Analysis of FIR Filter Design Using Modified
Truncation Multiplier with SQRT based Carry Select Adder”, IJET, vol 7, no 2.32(2018).
 Deepika, Nidhi Goel, “Design of FIR filter Using Reconfigurable MAC Unit”, © 2017 IEEE.
 Mahvish Quraishi, V.D. Alagd- eve, “Energy efficient reconfigurable fir filter architecture” ©
2017 IEEE.
Thank you