IEEE - 40222
ASIC Implementation of Efficient
16-Parallel Fast FIR Algorithm Filter Structure
Swetha Annangi
Assistant Professor, Department of ECE
Guru Nanak Institute of Technology
Hyderabad, INDIA.
swetha1008.gnit@gmail.com
Abstract—In this paper, a 144-tap 16-parallel Fast Finite
Impulse Response (FIR) Algorithm (FFA) filter structure is
designed using verilog HDL. The designed filter structure is
simulated using XILINX ISE 14.7. The designed module is
synthesized using CADENCE RTL Compiler and the application
specific integrated circuit (ASIC) design of the proposed filter
structure is implemented using CADENCE tool set on
CADENCE GPDK45nm technology. By applying Fast FIR
Algorithm, 65 percent of multipliers are reduced and the number
of adders are increased. The adders occupy less silicon area than
multipliers. Hence, the reduction in area is achieved by replacing
the multipliers with adders. Further, the proposed 16 parallel
FFA filter structure reduces the delay when compared to 16
parallel FIR filter structure without applying Fast FIR
Algorithm. The proposed filter architecture occupies an area of
79220 sq. μm and consumes a power of 20mW at 333MHz when
synthesized.
Keywords—Finite Impulse Response (FIR), Fast FIR
Algorithm (FFA), Parallel FIR, Application Specific Integrated
Circuit (ASIC), Verilog HDL.
I. INTRODUCTION
The swift development of the digital signal processing
(DSP) in an area of science and technology is a result of
significant advances in digital computer technology and
integrated-circuit fabrication [11]. The rapid growth in VLSI
of electronic circuits has spurred the development of powerful,
smaller, faster and cheaper digital computers and special-
purpose digital hardware. These economical and analogously
quick digital circuits have made it possible to construct highly
sophisticated digital systems capable of performing complex
digital signal processing functions and tasks, which are usually
too hard and high cost to be performed by analog circuitry or
analog signal processing systems.
Keshab K. Parhi has designed 2, 3, 4, 6 and 8-parallel FFA
filter structures in [1]. In [2], David A. Parker and Keshab K.
Parhi have designed 12-parallel FFA filter structure by
cascading two 2-parallel and one 3-parallel FFA filter
structures. In this paper, efficient 16-parallel FFA filter
structure is designed and implemented.
This paper is organized as follows: A brief introduction
and classification of digital filters are explained in section II.
Section III describes about Parallel Fast FIR Algorithm. In
8th ICCCNT 2017
July 3-5, 2017, IIT Delhi
Delhi, India
Ravisankar Puli
Senior ASIC Design Engineer
First Pass Semiconductors Pvt. Ltd.
Hyderabad, INDIA.
ravis.puli80@gmail.com
section IV, implementation of 16-parallel FFA filter is
presented. Section V shows the simulation results, RTL
compiler synthesis schematic, standard cell placement and
place and route implementation of 16-parallel FFA filter
structure. In section VI, the conclusion and future work are
given.
II. DIGITAL FILTERS
Digital filter is a system that transforms a given sequence
of numbers into a second sequence that has some more
desirable properties, such as less noise or distortion. If the
sequence is generated by a microphone, the digital filter may
attempt to produce an output sequence having less background
noise or interference. In radar applications, these are used to
improve the detection of aero planes. In speech processing,
digital filters have been employed to reduce the redundancy in
the speech signal so as to allow more efficient transmission,
and for speech recognition. A digital filter uses a digital
processor to perform numerical calculations on sampled
values of the signal. The advantages of a digital filter are- it is
programmable, versatile, extremely stable, easily designed,
tested and implemented.
A digital filter consists of the interconnection of three
simple elements: adders, multipliers and delays. The adders
and multipliers are simple components that are accessibly
implemented in the arithmetic logic unit of the computer.
Delays are components that allow access to future and past
values in the sequence.
There are two basic types of digital filters- Finite Impulse
Response (FIR) and Infinite Impulse Response (IIR). FIR
filters do not have feedback. Whereas IIR filters have
feedback. FIR filters are important building blocks for various
DSP applications [6]. FIR filters are simple to design and
guaranteed to be bounded input-bounded output stable. The
popular applications of FIR filters are echo cancellation,
multi-path delay compensation, speech synthesis, waveform
synthesis, video processing, wireless communications security
and bio-medical signal processing.
An N-tap FIR filters in time domain [1], [2], [3], [5], [6],
[7], [8], [9] can be expressed as
 IEEE - 40222

(1)
Where {x(n)} is an infinite length input sequence and the
sequence {h(n)} contains the FIR filter coefficients of length
N.
III. PARALLEL FAST FIR ALGORITHM FILTER
(5)
The terms H0X0 and H1X1 are common and can be shared
for the computation of Y0 and Y1.
The 2-parallel fast FIR filter structure is shown in figure 2.

A. Parallel FIR Filter

Parallel processing can be applied to digital FIR filters to
either increase the effective throughput or reduce the power
consumption of the original filter [2]. In L-parallel FIR filter,
the L-output subsequences y(Lk+i) can be computed using
combination of L subfilters from the L input subsequences
x(Lk+i) as Figure 2: 2-Parallel FFA Filter Structure

IV. IMPLEMENTATION OF 16 PARALLEL FFA FILTER

(2) The larger block size parallel fast FIR filters can be
For 2-parallel FIR filter designed by cascading smaller size parallel fast FIR filters.
The 16-parallel FFA can be designed by cascading 2-parallel
FFA filter structures 4 times that gives 24=16 parallel FFA
filter structure.
(3)
The design of 16-parallel FFA filter is described below.
From the equation (3),
Substituting L=16 in equation (2),

(4)
Where Y0 and Y1 corresponds to y(2k) and y(2k+1) in
time domain respectively.
Figure 1 shows the resulting 2-parallel FIR filter structure.

(6)
(7)
The 16-parallel FFA filter structure is obtained by first
applying the 2-parallel FFA to equation (7).

Figure 1: 2-Parallel FIR Filter Structure

(8)
B. Parallel Fast FIR Algorithm (FFA) Filter Where
Fast FIR Algorithm (FFA) reduces the multiplications
required to produce reduced complexity parallel filtering
structures. With this algorithm, the L-parallel filter can be
implemented using (2L-1) filtering operations of length (N/L).
The resulting parallel filtering structure would require (2N-
N/L) multiplications. For example, if N=4, L=2, the
conventional 2-parallel approach require 8 multiplications
while 2 parallel fast FIR approach require only 6
multiplications [1].
The 2-parallel FIR filter equations in equation (4) can be
rewritten as [1], [2], [3], [5], [8], [9], [10], (9)

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 IEEE - 40222

Applying 2-parallel FFA second time to the filtering

operations in equation ((8))

The equations (9) are written as

(13)
Finally applying 2-parallel FFA fourth time to the filtering
operations which are obtained from third 2-parallel FFA
(10)
Where

The fourth application of the 2-parallel FFA leads to 16-

(11)
Further applying 2-parallel FFA third time to the filtering
operations which are obtained from second 2-parallel FFA
parallel FFA filter structure. The 16-parallel FFA filter outputs
Y0, Y1, Y2, Y3, Y4, Y5, Y6, Y7, Y8, Y9, Y10, Y11, Y12, Y13, Y14, Y15 can
be obtained from the equation which will obtain after applying
the final 2-parallel FFA.
V. RESULTS AND COMPARISON

A. Simulation Resuts
The 16 parallel 144-tap FFA filter structure with an 8-bit
input is designed using verilog HDL. The designed module is
simulated using Xilinx ISE 14.7 tool. The simulation results of
proposed 16-parallel FFA filter structure are obtained by
writing the test bench for the designed module and are shown
The equations (11) are written as in figure 3.

(12)
Where Figure 3: Simulation results

B. Implementation Results
RTL compiler is a powerful tool for logic synthesis and
analysis for digital designs. The designed proposed filter
module is synthesized using Cadence RTL compiler. The RTL
compiler synthesis schematic of the proposed filter is shown in
figure 4. The standard cell placement is a method of designing
ASICs with digital logic features. The standard cell placement
of the 16 parallel FFA filter structure is shown in the figure 5.
Place and route is composed of two steps placement and
routing. Placement involves deciding where to place all
electronic components, circuitry and logic elements. And

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 IEEE - 40222

routing decides the exact design of all the wires needed to

connect the placed components. The place and route
implementation of the proposed filter is shown in figure 6.

Figure 6: Place and Route

C. Comparison
The 16 parallel FFA filter structure and 16 parallel FIR
filter structure are designed using verilog HDL and
synthesized using RTL compiler. The comparison between 16
parallel Fast FIR Algorithm filter and the 16 parallel FIR filter
which are obtained from synthesis reports is shown in table 1.
From the comparison table it is shown that number of
multipliers required for 16 parallel FIR filter with Fast FIR
Algorithm is reduced when compared to 16 parallel FIR filter
structure. The delay is also reduced with the proposed filter
structure. The adders requirement has increased but it will not
Figure 4: RTL Compiler Synthesis Schematic
affect the design because adders occupy less silicon area when
compared to multipliers. The area and leaf instance count are
also mentioned in the comparison table.

TABLE I. COMPARISON TABLE

16 Parallel Proposed 16
Parameters
FIR Parallel FFA
Delay (ns) 4 3

Multipliers 256 90

Adders 240 465

Area (sq. μm) 118909 79220

Leaf Instance Count 37189 26859

Power (mW) 17 20

VI. CONCLUSION AND FUTURE WORK

Figure 5: Standard Cell Placement
The proposed 144-tap 16-parallel FFA filter structure with
a bit length of 8-bit is designed using Verilog HDL. The
designed module is simulated using XILINX ISE 14.7. The
designed module is synthesized using CADENCE RTL
Compiler. And ASIC implementation of 16 parallel FFA filter
structure has done on CADENCE GPDK45nm technology.
From the simulation and synthesis results, it is concluded that
the performance of the 16-parallel FFA filter is most efficient.
The multiplications requirement has reduced to 65%. The

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 IEEE - 40222

delay and area are also reduced in the proposed filter structure.
Hence, the proposed filter structure is useful for less area and
high speed applications. Further, this work can be extended
by increasing the parallel block size and different bit lengths.
REFERENCES
[1] K. K. Parhi, VLSI Digital Signal Processing Systems: Design and
Implementation. Newyork: Wiley, 1999.
[2] David A. Parker, Keshab K. Parhi, “Area-Efficient Parallel FIR Digital
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[3] Yu-Chi Tsao and Ken Choi, “Area-Efficient Parallel FIR Digital Filter
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[4] Arnob Paul, Tanvir Zaman Khan, Prajoy Podder, Md. Mehedi Hasan
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[5] D. Ashok Kumar, Maroju Sai Kumar, Dr. P. Samundeswari, “Design
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[6] Amita Nandal, T. Vigneswarn, Ashwani K. Rana and Arvind Dhaka, “
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[7] J. Selvakumar, S. Narendran, “FPGA Based Fast FIR Algorithm for
Higher Order Digital FIR Filter”, International Symposium on
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[8] S. A. Takalkar, Y. D. Borole, “Fast FIR Algorithm Based Parallel FIR
Digital Filter Structures for Symmetric Convolutions”, International
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[9] P. Thenmozhi, C. Thamilarasi and V. Venkateswaran, “Fast FIR
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[10] B. Divya, A. Azhagu Jaisudhan Pazhani, “New Architecture of Parallel
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[11] John G. Proakis, Dimitris K Manolakis, Digital Signal Processing
Priciples, Algorithms and Applications, Pearson, 2007.

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