Interleaved Push-pull

FYP
FINAL YEAR PROJECT
DC to DC Converter
F Y P P r e s e n t a ti o n
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Group Information
ADVISORS &MEMBERS

Members Advisor
• Abdul Malik Sardar 2016008 EEP • Dr. Hadeed Ahmed Sher
• Abdul Qadeer Khan 2016010 EEP
• Imad Khan 2016183 EEP Co-Advisor
• Shah Fahad 2016449 EEP • Dr. Shahid Alam

Interleaved Push-pull Converter 2

 Project Objectives
• DC to DC converter based on
Push-pull Topology
• Interleaved
• Power rating 250 W
• 48 V DC to 100 V DC
• Output voltage regulation with
±10% variation in input voltage

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FYP
FINAL YEAR PROJECT
Circuit Design
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Circuit Design
ACTUAL DESIGN

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Circuit Design
ACTUAL DESIGN

Governing Equations Output Filter

• Relationship between input and output • Inductor
voltages, duty cycle and turns ratio.

• Where
• Where is the inductance
is output voltage is the time period of PWM signal
is input voltage is the nominal output current
is the turns ratio is output voltage
is the duty cycle
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Circuit Design
ACTUAL DESIGN

Snubber Circuit
• RCD snubber circuit • Resistor
• Controlling voltage peaks
• Resistance is selected based on voltage
and current ratings • Capacitor
• Capacitor selected on the bases of
voltage rating and frequency

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Circuit Design
ACTUAL DESIGN

Transformer
• Relationship for transformer’s primary turns • Magnetizing inductance

• Where • Where
is input voltage
is core cross-sectional area
is the inductance
is the maximum magnetic flux is the number of turns
density is a value specified in the datasheet
is the switching frequency of the core selected
is the duty cycle

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Circuit Design
ACTUAL DESIGN

Transformer Output Filter

• Magnetizing Inductor = 240.1 μH • Inductor = 2 mH
• Leakage Inductance = 1 nH • Capacitor = 0.2 uF
• Np = 8
• Ns = 24 Design Specification
• Turn ratio = 3 • Duty Cycle = 35.7%
• Switching Frequency = 100 kHz

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Hardware

Transformer
• ETD 49/25/16 Ferrite Core
• Enameled copper wires
• 18 Primary center-tapped windings
• 48 Secondary center-tapped (2 in
parallel)
• 24 swg for secondary
• 17 swg for primary

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PWM Signal
M O S F E T G AT E D R I V E & F E E D B A C K

• 100 kHz Frequency

• 32% ≤ Duty Cycle ≤ 40%
• Two Signals with 180° Phase Shift
• LM 5033 for PWM signal
• Feedback using Arduino Nano

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Circuit Design
PWM SINGAL & FEEDBACK

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Duty Cycle VS Feedback Voltage
L M 5 0 3 3 D ATA S H E E T

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FYP
FINAL YEAR PROJECT
Simulation Results
Power Simulator
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Simulation Results
M O S F E T g a ti n g s i g n a l s & V o l t a g e s

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Simulation Results
M O S F E T g a ti n g s i g n a l s & Tr a n s f o r m e r w i n d i n g V o l t a g e

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Simulation Results
Inductor & Output current and voltage

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FYP
FINAL YEAR PROJECT
PCB Layout
EasyEDA
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PCB layout
Parameters

Software
•Primary side traces width = 1.5mm EasyEDA
•Secondary side traces width= 0.5 mm
•Control Circuitry trace width= 0.254mm
•PCB Board width=169mm x 92 mm
•PCB board Thickness = 1.6mm

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PCB Layout
Upper layer

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PCB Layout
Lower layer

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Thank You!