A tour of combinational circuit design concepts

Addition of Binary Numbers

Full Adder. The full adder is the fundamental building block
of most arithmetic circuits:   ai b i

Cout
Full Cin

Adder
si

The sum and carry outputs are described as:

si  ai bi ci  ai bi ci  ai bi ci  ai bi ci
ci 1  ai bi ci  ai bi ci  ai bi ci  ai bi ci  ai bi  ai ci  bi ci
VLSI Arithmetic 2
Addition of Binary Numbers
Inputs Outputs
ci ai bi si ci+1
0 0 0 0 0
0 0 1 1 0
Propagate
0 1 0 1 0
0 1 1 0 1 Generate
1 0 0 1 0
1 0 1 0 1
Propagate
1 1 0 0 1
1 1 1 1 1 Generate
VLSI Arithmetic 3
 Full-Adder Implementation
Full Adder operations is defined by equations:
si  ai bi ci  ai bi ci  ai bi ci  ai bi ci  ai  bi  ci  pi  ci
ci 1  ai bi ci  ai bi ci  ai bi  g i  pi ci ai bi

Carry-Propagate: pi  ai  bi
and Carry-Generate gi

g i  a i  bi
c ou t
c in
One-bit adder could be
implemented as shown

VLSI Arithmetic si 4
 High-Speed Addition
ci 1  g i  pi ci

ai bi
g i  ai  bi pi  ai  bi

0
c o ut
s 1 c in

One-bit adder could be

implemented more efficiently si  pi  ci
because MUX is faster si
VLSI Arithmetic 5
The Ripple-Carry Adder

VLSI Arithmetic 6
 The Ripple-Carry Adder
A0 B0 A1 B1 A2 B2 A3 B3

Ci,0 Co,0 C o,1 Co,2 Co,3

FA FA FA FA
(= C i,1)

S0 S1 S2 S3

Worst case delay linear with the number of bits

td = O(N)

tadder   N – 1 tcarry + tsum

Goal: Make the fastest possible carry path circuit

From Rabaey
VLSI Arithmetic 7
 Inversion Property
A B A B

Ci FA Co Ci FA Co

S S

S  A B C i  = S  A B  Ci 

C o  A B C i  = Co  A B  Ci 

From Rabaey
VLSI Arithmetic 8
Minimize Critical Path by Reducing Inverting Stages

Even Cell Odd Cell

A1 B1 A3 B3
A0 B0 A2 B2

Ci,0 C o,0 Co,1 C o,2 C o,3

FA’ FA’ FA’ FA’

S0 S2
S1 S3

Exploit Inversion Property

From Rabaey Note: need 2 different types of cells

VLSI Arithmetic 9
Symmetrical adder cell

VLSI Arithmetic 10
 Carry-Select Adder
O. J. Bedrij, “Carry-Select Adder”, IRE
Transactions on Electronic Computers, June
1962, p.340-34

VLSI Arithmetic 11
 Carry-Select Adder
Addition under assumption of Cin=0 and Cin =1.

Prof. V.G. Oklobdzija VLSI Arithmetic 12

 Carry Select Adder:
combining two 32-b VBAs in select mode

Delay =VBA32+ MUX

VLSI Arithmetic 13
Carry-Skip Adder
MacSorley, Proc IRE 1/61
Lehman, Burla, IRE Trans on Comp, 12/61

VLSI Arithmetic 14
 Carry-Skip Adder
P0 G1 P0 G1 P2 G2 P3 G3

Ci,0 C o,0 C o,1 Co,2 Co,3

FA FA FA FA

P0 G1 P0 G1 P2 G2 P3 G3
BP=P oP1 P2 P3
Ci,0 C o,0 Co,1 C o,2
FA FA FA FA

Multiplexer
Co,3

Bypass
Idea: If (P0 and P1 and P2 and P3 = 1)
From Rabaey
then C o3 = C 0, else “kill” or “generate”.
VLSI Arithmetic 15
 Carry-Skip Adder:
N-bits, k-bits/group, r=N/k groups

a N -1bN -1 a N -k -1b N -k-1 a b

(r-1)k (r-1)k a (r-1)kb (r-1)k a 2 k-1b 2k-1 a k b k a k-1 b k-1
a0 b 0

... ... ... ...

OR OR OR OR
C out + Gr + G r- ... + G1 + Go C in
1
... ... ... ... ... ... ... ...

S N-1 S S (r-1)k-1 S S Sk S S
N -k-1 (r-2)k 2k-1 k-1 0

P r-1 P r-2 P1 P0
...
AND AND AND AND
critical path, delay =2(k-1 )+(N /2-2)

VLSI Arithmetic 16
 Carry-Skip Adder
tp
ripple adder

bypass adder

N 
t d  2k  1t RCA    2 t SKIP
 2k 
4..8
N
VLSI Arithmetic 17
 Carry-Lookahead Adder
(Weinberger and Smith)

Weinberger and J. L. Smith, “A Logic for High-Speed

Addition”,
National Bureau of Standards, Circ. 591, p.3-12, 1958.

VLSI Arithmetic 18
 Carry-Lookahead Adder
(Weinberger and Smith)
ci 1  ai bi ci  ai bi ci  ai bi  g i  pi ci
c i  2  g i 1  p i 1 c i 1
 g i 1  p i 1 ( g i  p i c1 )
 g i 1  p i 1 g i  p i 1 p i c1
ci 3  g i  2  pi  2 ci  2
 g i  2  pi  2 ( g i 1  pi 1 g i  pi 1 pi ci )
 g i  2  pi  2 g i 1  pi  2 pi 1 g i  pi  2 pi 1 pi ci

VLSI Arithmetic 19
 Carry-Lookahead Adder
G j  g i 3  pi 3 g i  2  pi 3 pi  2 g i 1  pi 3 pi  2 pi 1c j
Pj  pi 3 pi  2 pi 1 pi a i+3 b i+3 a i+2 b i+2 a i+1 b i+1 ai bi

 
One gate delay  Cin Cj
 
to calculate p, g g i+1p i+1 g i+1p i+1 g i+1p i+1 gi pi

One to calculate C 4(j+1)

P and two for G P , G G roup

Three gate delays

C 4j+3 C 4j+2 C 4j+1
To calculate C4(j+1)
Gj Pj
c4 ( j 1)  Gi  Pi c4 j Compare that to 8  in RCA !
VLSI Arithmetic 20
 Carry-Lookahead Adder
(Weinberger and Smith)
G* j  Gi  3  Pi  3Gi  2  Pi  3 Pi  2Gi 1  Pi  3 Pi  2 Pi 1Gi
P * j  Pi 3 Pi  2 Pi 1 Pi
G j+3 P j+3 G j+2 P j+2 G j+1 P j+1 Gj Pj

 
 

C 4(j+1) C 4j
G* P*

c4 ( j 1)  G *k  P *k c4 j C 4j+3 C 4 j+2 C 4 j+1

Additional two gate delays

C16 will take a total of 5 vs. 32 for RCA !
VLSI Arithmetic 21
 32-bit Carry Lookahead Adder
individ ual add ers
ai gen erating: g i, p i, bi
and sum S i

C 28 C 24 C 20 C 12 C8 C4
C in

C 16
C out C in

C a rry-loo ka head su per- blocks of C out C in

C a rry-lookah ead blo cks of
4-b its b locks gen era ting: 4-b its generating:
G * i, P * i, an d C in for th e 4-bit G i, P i, and C in for the
blocks ad ders
G roup producing final
carry C out and C 16

C ritical pa th delay = (for gi,pi)+2x2  (for G ,P )+3x2  (fo r C in )+1 X O R - (fo r S um ) = a ppx. 12 o f d elay

VLSI Arithmetic 22
 Carry-Lookahead Adder
(Weinberger and Smith: original derivation )

VLSI Arithmetic 23
 Carry-Lookahead Adder
(Weinberger and Smith: original derivation )

VLSI Arithmetic 24