VLSI Arithmetic

Adders & Multipliers

 Introduction
• Digital Computer Arithmetic belongs to
Computer Architecture, however, it is also an
aspect of logic design.
• The objective of Computer Arithmetic is to
develop appropriate algorithms that are
utilizing available hardware in the most
efficient way.
• Ultimately, speed, power and chip area are
the most often used measures, making a
strong link between the algorithms and
technology of implementation.

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 Basic Operations

• Addition
• Multiplication
• Multiply-Add
• Division

• Evaluation of Functions
• Multi-Media

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Addition of Binary Numbers
 Addition of Binary Numbers
Full Adder. The full adder is the fundamental building block
of most arithmetic circuits:
ai bi

Cout Full Cin

Adder
si
The sum and carry outputs are described as:
si  ai bi ci  ai bi ci  ai bi ci  ai bi ci
ci 1  ai bi ci  ai bi ci  ai bi ci  ai bi ci  ai bi  ai ci  bi ci
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 Addition of Binary Numbers
Inputs Outputs
ci ai bi si ci+1
0 0 0 0 0
0 0 1 1 0
Propagate
0 1 0 1 0
0 1 1 0 1 Generate
1 0 0 1 0
1 0 1 0 1
Propagate
1 1 0 0 1
1 1 1 1 1 Generate

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 Full-Adder Implementation
Full Adder operations is defined by equations:
si  ai bi ci  ai bi ci  ai bi ci  ai bi ci  ai  bi  ci  pi  ci
ci 1  ai bi ci  ai bi ci  ai bi  g i  pi ci ai bi

Carry-Propagate: pi  ai  bi
and Carry-Generate gi

g i  a i  bi
c out
c in
One-bit adder could be
implemented as shown

si
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 High-Speed Addition
ci 1  g i  pi ci

ai bi
g i  ai  bi pi  ai  bi

0
c out
s 1 c in

One-bit adder could be

implemented more efficiently si  pi  ci
because MUX is faster
si
 The Ripple-Carry Adder

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 The Ripple-Carry Adder
A0 B0 A1 B1 A2 B2 A3 B3

Ci,0 Co,0 C o,1 Co,2 Co,3

FA FA FA FA
(= C i,1)

S0 S1 S2 S3

Worst case delay linear with the number of bits

td = O(N)

t adder   N – 1 t carry + tsum

Goal: Make the fastest possible carry path circuit

From Rabaey

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 Inversion Property

A B A B

Ci FA Co Ci FA Co

S S

S  A B C i  = S  A  B  C i 

C  A B C  = C  A B  C 
o i o i

From Rabaey

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 Minimize Critical Path by Reducing Inverting
Stages

Even Cell Odd Cell

A1 B1 A3 B3
A0 B0 A2 B2

Ci,0 C o,0 Co,1 C o,2 C o,3

FA’ FA’ FA’ FA’

S0 S2
S1 S3

Exploit Inversion Property

From Rabaey Note: need 2 different types of cells

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 Ripple Carry Adder
Carry-Chain of an RCA implemented using multiplexer from the
a i+2 library:
standard cell b i+2 a i+1 b i+1 ai bi

Critical Path
c i+1 ci
c out c in

Oklobdzija, ISCAS’88
s i+2 s i+1 si

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 Manchester Carry-Chain
Realization of the Carry Path
• Simple and very popular scheme for implementation of
carry signal path

V dd V dd V dd V dd V dd V dd V dd V dd

Generate
device
Carry out Carry in

+ + + + + + + + Propagate
device

Predischarge
& kill device

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 Original Design
T. Kilburn, D. B. G. Edwards, D. Aspinall, "Parallel Addition in Digital Computers:
A New Fast "Carry" Circuit", Proceedings of IEE, Vol. 106, pt. B, p. 464, September 1959.

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 Manchester Carry Chain (CMOS)
•Implement P with pass-transistors
•Implement G with pull-up, kill (delete) with pull-down
•Use dynamic logic to reduce the complexity and speed up
VDD


P0 P1 P2 P3 P4

Ci,0
G0 G1 G2 G3 G4

Kilburn, et al, IEE Proc, 1959.

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Pass-Transistor Realization in DPL
C C
VCC
S
A
A
B
B
S

X O R /X N O R M U LT IP LE X E R B UFFER

A N D /N A N D
VCC

A
A C C
B VCC
CO
B

VCC

A CO
A
B M U LT IP LE X E R B UFFER
B

O R /N O R

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 Carry-Skip Adder
MacSorley, Proc IRE 1/61
Lehman, Burla, IRE Trans on Comp, 12/61

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 Carry-Skip Adder
P0 G1 P0 G1 P2 G2 P3 G3

Ci,0 C o,0 C o,1 Co,2 Co,3

FA FA FA FA

P0 G1 P0 G1 P2 G2 P3 G3
BP=P oP1 P2 P3
Ci,0 C o,0 Co,1 C o,2
FA FA FA FA

Multiplexer
Co,3

Bypass
Idea: If (P0 and P1 and P2 and P3 = 1)
From Rabaey
then C o3 = C 0, else “kill” or “generate”.

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 Carry-Skip Adder:
N-bits, k-bits/group, r=N/k groups

a N -1bN -1 a N -k-1b N -k-1 a b

(r-1)k (r-1)k a (r-1)kb (r-1)k a 2k-1b 2k-1 a k b k a k-1 b k-1
a0 b 0

... ... ... ...

OR OR OR OR
C out + Gr + G r- ... + G1 + Go C in
1
... ... ... ... ... ... ... ...

S N-1 S S (r-1)k-1 S S Sk S S
N-k-1 (r-2)k 2k-1 k-1 0

P r-1 P r-2 P1 P0
...
AND AND AND AND
critical path, delay =2(k-1)+(N /2-2)

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 Carry-Skip Adder

tp
ripple adder

bypass adder

N 
t d  2k  1t RCA    2 t SKIP
 2k 
4..8
N
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 Variable Block Adder
(Oklobdzija, Barnes: IBM 1985)

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 Carry-chain of a 32-bit Variable Block Adder
(Oklobdzija, Barnes: IBM 1985)

a b aj bj a bi a0 b0
N-1 N-1 i
..
.. ... ... ... ..
.
C out
Gm G m -1 G m -2 G2 G1 G0 C in

S N-1 Sj Si S0

Pm P m -1 P m -2 P2 P1 P0

Gm G m -1 G m -2 ... G2 G1 G0
skiping
...
C ou C in
t
Carry signal path
rippling

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Carry-chain of a 32-bit Variable Block Adder
(Oklobdzija, Barnes: IBM 1985)

6
5 5
4 4
1 3 =9 3 1

Any-point-to-any-point delay = 9 
as compared to 12  for CSKA

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Carry-chain block size determination for a
32-bit Variable Block Adder
(Oklobdzija, Barnes: IBM 1985)

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Delay Calculation for Variable Block Adder
(Oklobdzija, Barnes: IBM 1985)

P0 P1 P2 P3 BP
Ci,0 Co,3
G0 G1 G2 G3

BP

Delay model:

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 Variable Block Adder
(Oklobdzija, Barnes: IBM 1985)

Variable Group Length

td  c1  c2 N  c3

Oklobdzija, Barnes, Arith’85

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Carry-chain of a 32-bit Variable Block Adder
(Oklobdzija, Barnes: IBM 1985)

Variable Block Lengths

• No closed form solution for delay

• It is a dynamic programming problem

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Delay Comparison: Variable Block Adder
(Oklobdzija, Barnes: IBM 1985)

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Delay Comparison: Variable Block Adder

Delay 16

14 VBA
12

CLA
10

8
VBA- Multi-Level
6

0
4 11 18 25 32 39 46 53 60
Size N

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