Arithmetic circuits

Bit-Sliced Design
Control

Bit 3

Data-Out
Multiplexer
Bit 2
Data-In

Register

Adder

Shifter
Bit 1
Bit 0

Tile identical processing elements

2
 The simplest method of
A0 B0 A1 B1 A2 B2 A3 B3 addition of two binary
numbers is the carry-
propagate addition.
Ci,0 Co,0 Co,1 Co,2 Co,3
FA FA FA FA
(= Ci,1) starting from the least
significant bit, and carries
are propagated from a bit-
S0 S1 S2 S3 stage to the adjoining
more significant bit-stage.
S = A EXOR B EXOR Cin
Co = AB + BCin + CinA

An N bit adder is constructed by cascading N full-adder (FA) circuits

in series connecting Co,k-1 to Ci,k for k = 1 to N-1, and the first carry-
in Ci,o to 0
 The delay is proportional to the number of bits in the
input word N and is approximated by (worst case)

 tadder = (N-1) tcarry + tsum

 The propagation delay of the ripple carry adder is

linearly proportional to N. This property becomes
increasingly important when designing adders for
wide datapaths.

 Optimize tcarry and tsum

 Binary Full Adder

A B Ci S Co S = A EXOR B EXOR Cin

0 0 0 0 0 Co = AB + BCin + CinA
0 0 1 1 0
0 1 0 1 0 Logic manipulation to
0 1 1 0 1 reduce transistor count.

1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
 VDD

VDD
Ci A B

A B
A

B
Ci B
VDD
A
X
Ci

Ci A S
Ci

A B B VDD
A B Ci A

Co B
 NMOS and PMOS transistors connected to Ci are placed close to
output of the gate. Transistors on the critical path should be
placed as close as possible to the output of the gate.

 For instance in stage k of the adder, signals Ak and Bk are available

and stable long before Ci,k(=Co,k-1) arrives rippling through
previous stages. Thus capacitances of the internal nodes in the
transistor chain are pre charged or discharged in advance.

 On arrival of Ci,k the capacitance at node X has to be

(dis)charged

 Putting Ci,k transistors close to GND and VDD would require

not only (dis)charging of the capacitances of node X but also
internal capacitances.
Number of inverting stages in the carry path can be
reduced by exploiting the inverter property-
inverting all inputs of a full adder cell also inverts all
the outputs.

This allows to eliminate an inverter in a carry chain.

Inverting all inputs to a full adder results in inverted values
for outputs. S’ (A,B,Ci) = S (A’,B’,Ci’) ; Co’(A,B,Ci) =
Co(A’,B’,Ci’)

A B
A B

Ci FA
Co Ci FA
Co

S
S
Inverter in the carry chain eliminated.
 Even cell Odd cell

A0 B0 A1 B1 A2 B2 A3 B3

Ci,0 Co,0 Co,1 Co,2 Co,3

FA FA FA FA

S0 S1 S2 S3

Exploit Inversion Property

Arithmetic circuits so far

- Ripple carry adder

- Logic manipulation to help reduce transistor count
- Ordering input signals
- Exploiting inversion property
 Binary Full Adder

A B Ci S Co Carry Status
0 0 0 0 0 D (delete)
0 0 1 1 0 D (delete)
0 1 0 1 0 P (propagate)
0 1 1 0 1 P (propagate)
1 0 0 1 0 P (propagate)
1 0 1 0 1 P (Propagate)
1 1 0 0 1 Generate
1 1 1 1 1 Generate
Co = G + PCi , S = P EXOR Ci
G = 1 (D = 1) ensures carry generated (deleted)
at Co independent of Ci

P = 1 ensures carry propagates to Co

G = AB
D = A’B’
P = A EXOR B

Co(G,P) = G+ P Ci
S(G,P) = P EXOR Ci
A Better Structure: The Mirror Adder

VDD

VDD VDD A

A B B A B Ci B
Kill
"0"-Propagate A Ci
Co
Ci S
A Ci
"1"-Propagate Generate
A B B A B Ci A

24 transistors
 The Mirror Adder
 The NMOS and PMOS chains are completely symmetrical.
A maximum of two series transistors can be observed in the
carry-generation circuitry. Self duality of sum and carry.
 When laying out the cell, the most critical issue is the
minimization of the capacitance at node C’o.
 The capacitance at node C’o is composed of four diffusion
capacitances, two internal gate capacitances and six gate
capacitances in the connecting adder cell .
 The transistors connected to Ci are placed closest to the
output.
 Only the transistors in the carry stage have to be optimized
for optimal speed. All transistors in the sum stage can be
minimal size.
 Mirror Adder
Stick Diagram
VDD

A B Ci B A Ci Co Ci A B

Co

GND
 VDD
VDD Pi
Pi 
Gi Co
Ci
Co
Ci
Gi
Di
Pi


Manchester Carry gates.

Ci to Co if propagate is true.
If P is not true the output is either pulled low by Di or pulled up by Gi’

Dynamic version given in (b) Precharge eliminates the need for kill signal for
the case wherein the carry chain propagates the complimentary values of the
carry signal.
A Manchester carry chain uses a cascade of
pass transistors to implement the carry
chain.
 VDD

P0 P1 P2 P3
C3

Ci,0
G0 G1 G2 G3

C0 C1 C2 C3

(During precharge phase  = 0, all intermediate nodes charged to VDD. During

evaluation Ak node discharged when there is an incoming carry and the
propagate is high, or when generate is high.)
Carry Bypass Adder.

Po Go P1 G1 P2 G2 P3 G3

Co,1 Co,0
Co,0

Ci,0 Co,3
Carry propagation
Suppose that the values of Ak and Bk (k=0..3) are such that all
propagate signal are high (Pk for k = 0….3).

An incoming carry Ci,0 = 1 propagate under those conditions

through the complete adder chain and causes an outgoing carry
C0,3 = 1.

If(P0P1P2P3 = 1) then Co,3 = Ci,0

else either delete or generate occurred.

 Use MUX with BP = P0P1P2P3 = 1 as select line.

- carry bypass adder. (carry skip adder)

If this is not the case then carry by normal route.
BP=P0P1P2P3

P0 G0 P1 G1 P2 G2 P3 G3

Co,1 Co,2
Ci,0 Co,0
FA FA FA FA
M
U
X
Carry generated at the first bit position ripples through the
first block, skips around (N/M -2) by pass stages and is
consumed at the last stage without generating output carry
tadder = tsetup + Mtcarry + (N/M-1)tbypass + (M-1)tcarry + tsum

tsetup – fixed overhead time to create generate and propagate signals

tcarry – propagation delay through single bit. worst case delay through
single stage is of M bits.

tbypass – delay through bypass multiplexer of a single stage

tsum – time to generate sum on the final stage.

Arithmetic circuits so far

- Ripple carry adder

- Logic manipulation to help reduce transistor count
- Ordering input signals
- Exploiting inversion property
- Mirror adder
- Manchester carry chain
- Carry by pass adder
In ripple carry adder every full adder has to wait for the
incoming carry before an outgoing carry can be generated.

Anticipate both possible values of carry input and evaluate the

result for both the possibilities in advance.

Once real value of the incoming carry is known correct result

is selected with MUX stage.

Carry select adder

Linear Carry select adder

SETUP
P,G
0 0-carry propagation

1 1-carry propagation

Co,k-1 Co,k+3
multiplexer

Sum generation

Block of adders adding bits k to k+3

 16-bit, linear carry select adder.

Bit 0-3 Bit 4-7 Bit 8-11 Bit 12-15

setup setup setup setup

0 0 carry 0 0 carry 0 0 carry 0 carry

1 1 carry 1 1 carry 1 1 carry 1 carry

Ci,0
multiplexer multiplexer multiplexer multiplexer

Sum generation Sum generation Sum generation Sum generation

S0,3 S4,7 S8,11 S12,15

Worst case propagation delay of the module is

tadd = tsetup + Mtcarry + (N/M) tmux + tsum

N and M represent the total number of bits and the

number of bits per stage.

tcarry is delay of carry through a single full adder cell.

BITS Pilani, Pilani Campus

 Bit 0-3 Bit 4-7 Bit 8-11 Bit 12-15
setup setup setup setup
(1)
0 0 carry 0 0 carry 0 0 carry 0 carry

1 1 carry 1 1 carry 1 1 carry 1 carry

(5) (5)
Ci,0 (6) (7) multiplexer (8) multiplexer
multiplexer multiplexer

(9)
Sum generation Sum generation Sum generation Sum generation

S0,3 S4,7 S8,11 S12,15

Square Root Carry-Select Adder.

-Progressively adding more bits to the subsequent stages in

the adder.

For ex: first stage with 2 bits, second stage with 3 bits,
third with 4 bits ….

Annotated arrival times is faster than the linear

organization.
 Bit 0-1 Bit 2-4 Bit 5-8 Bit 9-13
setup setup setup setup
(1)
0 0 carry 0 0 carry 0 0 carry 0 carry

1 1 carry 1 1 carry 1 1 carry 1 carry

(3) (4) (5) (6)
Ci,0 (4) (5) multiplexer (6) multiplexer
multiplexer multiplexer

(7)
Sum generation Sum generation Sum generation Sum generation

S0,3 S4,7 S8,11 S12,15