MINI PROJECT – II

ON
AUTOMATIC WASHING MACHINE

Submitted by :
Shubham Rai(201300033)
Abhishek Rathour(201500022)
Project Guide:
Dr. Manish Gupta(Assistant Professor)
Project Incharge:
Dr. Divya Singh(Assistant Professor)
Department of Electronics & Communication Engineering
GLA University, Mathura(Uttar Pradesh)
OBJECTIVE

 Review of Verilog HDL for

digital design.
 To design electronic voting
machine using the concept of
FSM in HDL Verilog.
 To generate RTL schematic.
 Design Flow

System Architectural
RTL Modeling
Specification Design

Simulation
FINITE STATE MACHINE (FSM)
EVM Description
 The proposed digital EVM was designed using Verilog HDL and
implemented on Spartan 3 FPGA.
 The proposed method consists of 3 stages;
 First stage:
 we decide the total no. of voters and the total number of contestants
taking part in the election process.

 Second stage:
 voting process:- begins when the voter casts his vote to a particular
party or contestants the polled vote is registered in the individual
contestant registry.
Contd…
 Third stage:

 Votes compared:- after completion of voting process the votes are

validated by comparing the votes polled to the contestants with their
registries after which the election.

 The above proposed method can be implemented on FPGA

 it has the advantage that it can be reprogrammed over and over for
different tasks, making them very cost efficient by avoiding recurring
expenses.
 SCHEDULE

Division of the work Sep 2022 Oct 2022 Nov 2022 Dec 2022

Theory        

System specification        

Verilog module and testbench        

implementation

Simulation and Verification        

Completed Partially Done Not Completed

 REFERENCES

 Hossain, T., Uddin, S.S.S., Rokon, I.R., Salam, K.M.A. and Abdul, M., 2014.
Proficient FPGA Execution of Secured and Apparent Electronic Voting Machine
Using Verilog HDL. International Journal of Envirnment41, pp.18-24.
 
 Tripathi, R. and Kumari, A., 2020. FPGA Implementation of Biometric EVM
using AADHAAR Authentication. Journal of Innovation in Electronics and
Communication Engineering, 10(2), pp.7-10.
THANK YOU