Fabrication

Lecture 2
CMOS Processing &

Fabrication
Pradondet Nilagupta
pom@ku.ac.th
Department of Computer Engineering
Kasetsart University
Acknowledgement
 This lecture note has been summarized from
lecture note on Introduction to VLSI Design,
VLSI Circuit Design all over the world. I can’t
remember where those slide come from.
However, I’d like to thank all professors who
create such a good work on those lecture
notes. Without those lectures, this slide can’t
be finished.
2
204424 Digital Design Automation January 19, 2023
N Transistor Structure Review
Polysilicon Gate
SiO2
Insulator L D D
W
Source Drain
G SB G
n+ n+
channel
p substrate S S
substrate connected
n transistor to GND
3
P Transistor Structure Review
Polysilicon Gate
SiO2
Insulator L D
W
Source Drain
G SB G
p+ p+
channel
n substrate S substrate connected

to VDD
p transistor
4
Semiconductor Review
 Create by doping a pure silicon crystal
 Diffuse impurity into crystal lattice
 Changes the concentration of carriers
 Electrons
 Holes
 More doping -> more carriers available

 n-type semiconductor (n or n+)
n+
n
 Majority carrier: electrons
 Typical impurity: Arsenic (Column V)
 p-type semiconductor (p or p+) p+
 Majority carrier: holes
 Typical impurity: Boron (Column III)
5
Other key working materials
 Insulator - Silicon Dioxide (SiO2)
 Used to insulate transistor gates (thin oxide)
 Used to insulate layers of wires (field oxide)
 Can be grown on Silicon or Chemically Deposited
 Polysilicon - polycrystalline silicon
 Key material for transistor gates
 Also used for short wires
 Added by chemical deposition
 Metal - Aluminum (…and more recently Copper)
 Used for wires
 Multiple layers common
 Added by vapor deposition or “sputtering”
6
CMOS Processing
 Wafer Processing
 Photolithography
 Oxide Growth & Removal
 Material Deposition & Removal
 Diffusion of Impurities
 Putting it all together
7
A View of the Cleanroom
AMD’s Dresden Fab - Source: AMD Corporation www.amd.com
8
Creating Wafers - Czochralski
Method
 Start with crucible of
molten silicon
(≈1425oC)
 Insert crystal seed in
melt Molten
 Slowly rotate / raise Crucible Silicon
seed to form single

crystal boule
 After cooling, slice
boule into wafers &
polish
9
Definitions
 Wafer – a thin circular silicon
 Each wafer holds hundreds of dies
 Transistors and wiring are made from many layers
(usually 10 – 15) built on top of one another
 the first half-dozen or so layers define transistors
 the second define the metal wires between transistors
 Lambda () – the smallest resolvable feature size

imprinted on the IC;
it is roughly half the length of the smallest transistor
 0.2m IC – the smallest transistors are
approximately 0.2m in length (= 0.1m)
10
Wafer Structure
 Current production:
200mm (10”)
 Newest technology:
300mm (12”)
Die - Single IC chip
300mm wafer
Image Source: Intel Corporation
www.intel.com
11
Processing Wafers
 All dice on wafer processed simultaneously
 Each mask has one image for each die
 The basic approach:
 Add & selectively remove materials
 Metal - wires
 Polysilicon - gates
 Oxide
 Selectively diffuse impurities

 Photolithography is the key
12
Fabrication processes
 IC built on silicon substrate:
 some structures diffused into substrate;
 other structures built on top of substrate.
 Substrate regions are doped with n-type and
p-type impurities. (n+ = heavily doped)
 Wires made of polycrystalline silicon (poly),
multiple layers of aluminum (metal).
 Silicon dioxide (SiO2) is insulator.
13
Photolithography
 Coat wafer with photoresist
(PR)
 Shine UV light through
mask to selectively expose
UV Light
PR Mask
 Use acid to dissolve Photoresist
exposed PR Wafer
 Now use exposed areas for

 Selective doping
 Selective removal of material
under exposed PR
14
Adding Materials
 Add materials on top of
silicon Added Material
(e.g. Polysilicon)
 Polysilicon
 Metal
 Oxide (SiO2) - Insulator
Silicon
 Methods
 Chemical deposition
 Sputtering (Metal ions)
 Oxidation
15
Oxide (Si02) - The Key Insulator
 Thin Oxide
 Add using chemical deposition
 Used to form gate insulator & block active areas
 Field Oxide (FOX) - formed by oxidation
 Wet (H20 at 900oC - 1000oC) or Dry (O2 at 1200oC)
 Used to insulate non-active areas
SiO2 Thin Oxide FOX SiN / SiO2 FOX
Silicon Wafer Silicon Wafer
16
Patterning Materials using
Photolithography
 Add material to wafer
 Coat with photoresist Added Material
(e.g. Polysilicon)
 Selectively remove
photoresist
 Remove exposed Silicon
material
 Remove remaining PR
17
Diffusion
 Introduce dopant via
epitaxy or ion implant Blocking Material
e.g. Arsenic (N), Boron (Oxide)
(P)
 Allow dopants to diffuse Diffusion
at high temperature
 Block diffusion in Silicon
selective areas using
oxide or PR
 Diffusion spreads both
vertically, horizontally
18
CMOS Well Structures
 Need to accommodate both N, P transistors
 Must implement in separate regions - wellls
(tubs)
 N-well
 P-well
 Alternate approach: Silicon on Insulator (SOI)
n well p well n epi p epi
p substrate n substrate n tub p tub insulator
n-well p-well twin-tub SOI
19
Detailed View - N-Well Process
 Overall chip doped as p substrate, tied to
GND
 Selected well areas doped n, tied to VDD
Gnd VDD
n+ n+ p+ p+
channel channel
p substrate n well
20
CMOS Processing - Creating an
Inverter
 Substrate
 Well
 Active Areas
 Gates
 Diffusion
 Insulator
 Contacts
 Metal P substrate
n well
wafer
21
CMOS Mask Layers
 Determine placement of
layout objects
 Color coding specifies
layers
 Layout objects:
 Rectangles
 Polygons
 Arbitrary shapes
 Grid types
n well
 Absolute (“micron”) P substrate
 Scaleable (“lambda”) wafer
22
Mask Generation
 Mask Design using Layout Editor
 user specifies layout objects on different layers
 output: layout file
 Pattern Generator
 Reads layout file
 Generates enlarged master image of each mask layer
 Image printed on glass reticle
 Step & repeat camera
 Reduces & copies reticle image onto mask
 One copy for each die on wafer
 Note importance of mask alignment
23
Simple cross section
SiO2 metal3
metal2
transistor metal1
via
poly
n+ n+
p+
substrate
substrate
24
Transistor structure
n-type transistor:
25
0.25 micron transistor (Bell Labs)
gate oxide
silicide
source/drain
poly
26
Metal Layers
27
Current Trends in Fabrication
 Copper Interconnect
 Low-k dielectric for interconnect
 High-k dielectric for transistor gates
 Optical problems (and attempted fixes)
28
Copper interconnect
 Copper is a much better conductor than aluminum
 But, it tends to chemically react w/ silicon, oxide
 Fabrication of copper wires: “damascene” process
 Etch trenches in the surface where wires will be placed
 Coat with “secret chemical” (isolates Cu, silicon, oxide)
 Coat with layer of copper
 Polish wafer to remove copper except in trenches
29
Alternative Dielectrics
 Dielectric constant of SiO2: 3.9
 Problem: want to minimize coupling capacitance
between wires
 Solution: “low-k” dielectrics (featured in 130nm and
below)
 Proposed materials would have approx K=3
 Problem: want to maximize electric field under
transistor gates
 Solution: “high-k” dielectrics (anticipated in 90nm and
below)
 Proposed materials would have K>>4
30
Optical Problems
 Most photolithography is done using UV with
248nm wavelength
 BUT… current geometries << 248nm =>
interference problems
 Fixes:
 Optical proximity correction (OPC)
 Phase-shifting masks
 Other light sources: 193nmUV, Extreme UV, X-
Rays
 E-beam lithography
31
Example - Phase Shifting Masks
 Normal mask - light spreads & overlaps
 Phase shifting mask - cancels overlap
 Drawback: requires 2 masks per litho. step
(Expensive)
Graphic source: Numerical Technologies www.numeritech.com
32
After Fabrication- Testing and
Packaging
Figure Source: D. Patterson and J. Hennessey, Computer Organization and Design, Morgan Kafumann, 1996
33
Fabrication Example - MOSIS
Tiny chip
Photo Source:
R. Feiller ‘02
34
Fabrication services
 Educational services:
 U.S.: MOSIS
 EC: EuroPractice
 Taiwan: CIC
 Japan: VDEC
 Foundry = fabrication line for hire.
 Foundries are major source of fab capacity today.
35

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Lecture 2

CMOS Processing &

n substrate S substrate connected

 More doping -> more carriers available

AMD’s Dresden Fab - Source: AMD Corporation www.amd.com

seed to form single

 the second define the metal wires between transistors

 Lambda () – the smallest resolvable feature size

 Selectively diffuse impurities

 Now use exposed areas for

Silicon Wafer Silicon Wafer

Graphic source: Numerical Technologies www.numeritech.com

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