7/18/2014

Digital System Design with PLDs and FPGAs

Programmable Logic Devices

Kuruvilla Varghese
DESE
Indian Institute of Science
Kuruvilla Varghese

Introduction 2

• Idea: Memory as Programmable Logic

00 0 Address lines as inputs

X A1
01 1 Data line as output
Y A0 10 1
11 0 Truth table is the content
D0
X XOR Y

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PROM 3

A1 A0 4 , 2 bits

A1/ A0/

A1/ A0

A1 A0/

A1 A0

D1
D0

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PROM: Programmable Read Only Memory 4

• Combinational Circuit: Program Truth Table

• Fixed AND, Programmable OR
• 2n Minterms (n-input AND gates)
• Sharing of Minterms by outputs
• Large Area because of 2n AND gates
• Can we reduce AND gates ?
– Yes, But should be programmable
– Then Minterms Product Terms (PLA)

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PLA: Programmable Logic Array 5

A1 A0

D1

D0

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PLA: Programmable Logic Array 6

• Programmable AND
• Programmable OR
• < 2n Product Terms (2n-input AND gates)
• Sharing of Product Terms by outputs
• Programming Overhead
• For a single output, programmable OR is not required, if one
can disable product terms

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PAL: Programmable Array Logic 7

A1 A0

O1

O2

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PAL: Programmable Array Logic 8

• Programmable AND
• Fixed OR
• < 2n Product Terms (2n-input AND gates)
• Dedicated Product Terms for outputs

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Evolution 9

– PROM: Programmable Read Only Memory

Fixed AND, Programmable OR

– PLA: Programmable Logic Array

Programmable AND, Programmable OR

– PAL: Programmable Array Logic

Programmable AND, Fixed OR
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PAL16L8

Kuruvilla Varghese Source: Texas Instruments Data sheets

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PAL16L8 11

Kuruvilla Varghese Source: Texas Instruments Data sheets

Input/Output structure 12

• Output
– Enable Tri-state
– Blow all input connections
of the control AND gate,
wired AND with pull up
• Input
– Disable Tri-state Gate
– Retain all connections of
control AND gate
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• Input/Output
– Program Control AND gate
with control product term
• Disable any AND gate
– Retain all input connections
• Cascade
– More than 7 Product Terms
• Feedback
– Latch

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Cascading 13

• 17 Product terms

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Cascading / 17 PT 14

Kuruvilla Varghese Source: Texas Instruments Data sheets

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Cascading / 17 PT 15

Kuruvilla Varghese Source: Texas Instruments Data sheets

Cascading 16

• 7+6+4 • Cascading
– 3 passes – Reduce the number of
– 3 section delays passes avoiding chain
– 8 Sections (7 + 6x7 = 49
PTs), 8 passes
• (7 + 7) + 3
– 2 passes
– 2 section delays
– 8 sections (7 x 7 = 49 PT), 2
passes
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Simple PLD’s 17

• Devices • Feature
– PAL16L8 x – Wide Decoding
– PAL16R4 x – e.g. AND Gate with 16
– PAL16R8 x inputs, and 16
– PAL22V10 complements
– Earlier used for Chip select
• Manufacturers decoding of memory and
– Atmel peripherals
– Higher order address bits
were decoded

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Present Day Scenario 18

CS • Present Day SoC’s have

Deco
der • Built in RAM, Peripherals
Micro Address Peripher
Processor als
• Built in Configurable Chip
Control
Select decoding
Data
• Less use of SPLD’s like
PAL16L8

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Present Day Scenario 19

• Serial Interface for external

Serial Clock
peripherals
• Clock, data
Micro
Data Peripheral • Multiple Slaves
Processor
• Address part of Data Frames
• Read / write
• Multiple Masters, Arbitration
• SPI, I2C

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PAL16R4

Source: Texas Instruments Data sheets

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PAL16R4 21

Kuruvilla Varghese Source: Texas Instruments Data sheets

Datapath 22

D Q D Q
Comb
CLK CLK

clk

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Datapath => PAL 23

FF/Reg
Input

FF/Reg
Comb

Ouput
Input

Input

Kuruvilla Varghese Source: Texas Instruments Data sheets

FSM 24

Outputs
Inputs NS
Next
State D PS Output
Logic CK Q Logic
AR

Clock
Reset

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FSM => PAL 25

Input

FF/Reg
NSL

Input

OL
Output
Input

Kuruvilla Varghese Source: Texas Instruments Data sheets

FSM 26

Outputs

Inputs
NS D PS
Logic CK Q
AR

Clock
Reset

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FSM => PAL 27

Input

FF/Reg
Logic

Input

Logic
Output
Input

Kuruvilla Varghese Source: Texas Instruments Data sheets

Substitution 28

• Substitution
– x = ab/ + cd
2 PT’s 1 pass delay
– y = x + ef + ghi/
3 PT’ s 2 pass delay
• Substitute x in y
– y = ab/ + cd + ef + ghi/
4 PTs 1 Pass delay
• Virtual Substitution
– Uses unused PTs
– Reduces delay

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Substitution 29

Kuruvilla Varghese Source: Texas Instruments Data sheets

Substitution 30

• Pathological case: xor • Attribute to turn of virtual

a xor b = ab/ + a/b 2 PTs substitution
a xor b xor c 4 PTs
a xor b …xor n 2n-1
PTs

• Priority Encoders
• Adders/Subtractors

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PAL22V10

Kuruvilla Varghese Source: Texas Instruments Data sheets

PAL22V10 - Macrocell 32

Kuruvilla Varghese Source: Texas Instruments Data sheets

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PAL22V10 33

• Variable Product Terms • PT Optimization

• Asynchronous Reset – Y = A/C + AB + BC + AC/
Product Term – Y/ = AB/C + A/C/
• Synchronous Preset • Timing
Product term – tpd
• Combinational / Registered – ten, tdis
output – tcq, ts, th, tres
• Product Term Optimization – With / without feedback
by Inversion
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PLD 22V10 Fitting 34

• Is it possible to implement an 8 bit odd parity generator in a PLD

22V10 ? i.e. parity generator has 8 data inputs and one parity
output
• One has to check the following I/O requirements and product term
requirements.
• No: of inputs = 8 < 12 dedicated inputs of 22V10
• No: of outputs = 1 < 10 I/Os of 22V10
• Ex-or of n variables results in 2n-1product terms.
• We assume tool expands the EXOR’s to complete product terms
than implementing with Internal nodes.
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PLD 22V10 Fitting 35

• For 8 data inputs odd parity generator, Number of product terms

are 128 (We need to compute the product terms as PLD22V10
doesn’t have XOR gates)
• Now PLD 22V10 has (2 x 16 + 2 x 14 + 2 x 12 + 2 x 10 + 2 x 8) =
120 product terms among 10 outputs.
• For cascading we need a Macro cell/section with at least 9 product
terms, so we need to use a macro cell with 10 sections, this leaves
us with 110 product terms.
• Hence, the product term resources aren’t enough.

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PLD 22V10 Fitting 36

• This assumes that cascaded terms are substituted. If there is no

product term substitution, it is possible to fit, if any of the
following options are chosen
– cascade of 7 ex-or gates with 6 internal nodes
– log structure of 2 input exor gates 9
– log structure of 3 input exor gates
– log structure of 2, 4 input exor gates with second stage of 1, 2 input exor
gates.
– different cascaded schemes in which fewer than 7 exor gates are
substituted.

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Applications of SPLD 37

• Glue Logic
• Counter
• FSM
• Wide decoding is not required for many
applications
• Less FFs

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Programming Technology 38

• Fuse
• EPROM (UV Erasable)
• EEPROM
• Flash

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EPROM Transistor 39

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PAL16L8 40

Kuruvilla Varghese Source: Texas Instruments Data sheets

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EPROM Transistor Wired-AND 41

Wired NOR, Invert the inputs
Wired OR

A
Y
B

A
Y
B
I1/ (I1) I2/ (I2) In/ (In)

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EPROM Transistor Wired-AND 42

• Programmable AND
– Wired NOR with inputs using complements
– Transistors are EPROM
– When programmed, No connection
• Fixed OR
– Wired NOR followed by Inverter
– Normal n-type transistors are used

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Flash / EEPROM Transistor 43

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Flash Cell Write 44

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Flash Cell Erase 45

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EEPROM/Flash Transistor Wired-AND 46

Wired NOR, Invert the inputs Wired OR

Vdd Vdd Vdd

I1/ (I1) I2/ (I2) In/ (In)

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Programming SPLD’s 47

• Programming Interface
– JEDEC File, standard, ASCII
– Fuse patterns in 0 & 1
• Programming methodology
– Proprietary, uses the normal pins
– High voltage - switch to programming mode
– Address, data, read/write, program pins
– Blank check, verification, security
– UV/Electrically Erasable, Programmer
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Complex PLD (CPLD) 48

• Not a big SPLD, as the SPLD already has wide product

terms.
• What is sensible is multiple SPLD’s interconnected, such
that blocks of a medium sized design can fit in to these
SPLD blocks.
• Interconnection requirements.
– Output of any block should be able to go to one or more
inputs of any other blocks.
– Any input signal should be able to go to one or more inputs
of any blocks.
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Complex PLD (CPLD) 49

• Hierarchical PLD
• Product term array
• Product term Allocator / Distributor
• Macrocells
• I/O cells
• Programmable Interconnect

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PAL22V10

Kuruvilla Varghese Source: Texas Instruments Data sheets

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CPLD Manufacturers 51

• Xilinx
– XC9500XL, CoolRunner-II
• Altera
– Max 3000A, Max 7000S, Max II, Max V
• Atmel
– ATF15xx
• Lattice Semiconductor
– ispMACH 4000ZE

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MAX7000 CPLD 52

Kuruvilla Varghese Source: Altera Data sheets

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PIA: Programmable Interconnect Array 53

• Cross bar switch satisfying the connectivity requirements

discussed before.
• N x N cross bar can be implemented using, N, N-to-1
Multiplexers.
• Interconnection between blocks using just one switch.
• Simple timing, fast.
• Cross bar don’t scale well

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2 x 2 Crossbar 54

I0

I1

S0 S1

O0 O1

• N x N crossbar requires N, N to 1 Multiplexers

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MAX7000 Features 55

Kuruvilla Varghese Source: Altera Data sheets

Xilinx XC9500 Crossbar (Fast CONNECT) 56

Kuruvilla Varghese Source: Altera Data sheets

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MAX7000 Macrocell 57

Kuruvilla Varghese Source: Altera Data sheets

Clock Enable 58

0 D Q
D Q
1
CE

CK
CK

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Logic Block Features 59

• 5 PT’s per Macrocell

• D/T Flip-flop. Flip flop can be bypassed for combinational
output.
• XOR Gate: Polarity control, PT optimization, Comparator,
Arithmetic circuits, Parity
• PT set, PT Reset,
• Global Clock, PT Clock
• PT Clock enable

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MAX7000S Macrocell Fast Input 60

Kuruvilla Varghese Source: Altera Data sheets

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MAX7000 CPLD 61

Kuruvilla Varghese Source: Altera Data sheets

Fast Input 62

• Fast input architecture allows direct connection of

input to the Macrocell flip-flop through 2 to 1 Mux
at the input of flip-flop

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MAX7000S Macrocell Fast Input 63

Kuruvilla Varghese Source: Altera Data sheets

Fitting: VHDL Code 64

process (clk, rst)

begin
if (rst = ‘1’) then q <= ‘0’;
elsif (clk’event and clk = ‘1’) then
if (en = ‘1’) then
q <= a xor b;
end if;
end if;
end process;

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Fitting: Synthesized Circuit 65

0
a q q
d

1
b q
en
clk clk
rst
rst

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Fitting in CPLD 66
rst clk

q
b
a

en

Kuruvilla Varghese Source: Altera Data sheets

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Xilinx XC9500 Product Term Allocator 67

Kuruvilla Varghese Source: Xilinx Data Sheet

Product Term Allocator 68

• Demultiplexers let the PT’s to be allocated for various

functions like XOR input, PT clock, PT clock enable, PT
Set, PT Reset and PT Steering.
• 5 input OR gate with associated steering circuit allows the
unused PT’s in one section (combined with ones from
section above/below) to be steered to OR gate of the section
above or below.

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MAX7000S I/O Control Block 69

Kuruvilla Varghese Source: Altera Data sheets

MAX7000 Timing Model 70

Kuruvilla Varghese Source: Altera Data sheets

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CPLD vs FPGA 71

Features PLD FPGA

Logic AND-OR Mux / LUT / Gates

Register to Logic Small Large

ratio
Timing Simple Complex
Architecture Small Large
Variation
Programming Flash Anti-Fuse, SRAM
Technology

Capacity 10 K Few Million Logic

Cells + Few MB RAM
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CPLD Applications 72

• Small design comprising of counters, FSM, Small logic

• Examples
– Memory controllers (DRAM controller)
– Bus protocol translation (CPU Bus -> PCI Bus)
– Optical encoders.
– Small control circuit in Instrumentation, Power Electronics for
Data Acquisition control, Small digital control circuits.

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CPLD Applications 73

• Design which requires lot of registers and memory and

complex designs cannot be implemented.
– Signal processing architectures (Filters)
– Complex arithmetic circuits
– Communication circuits (Packet processing, Modems)
– CODEC’s
– Cryptographic circuits

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