VLSI Design I

CMOS Combinational Logic

Overview
Euler rules for complex CMOS gates
Layout and stick diagram

Goal: You know how to design compact layout of

complex CMOS logic gates with the Euler rules.
You are familiar with transmission gates and its
limitations.
MicroLab, VLSI-5 (1/34)

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 How ‘bout more than 1 input?
Vdd
Logic recipe:
pullup: make this connection
when we want F(A1,…,An) = 1
...

A1
F(A1,…,An)
...

An
pulldown: make this connection
when we want F(A1,…,An) = 0
...

Finally! I was
getting tired
of inverters...

we want VOH = Vdd, better use only

pfets in the pullup path
Š similarly, since we want VOL = 0, better
use only nfets in the pulldown path
Š looking at pulldown path: since nfets are
on when VGS > VTH, output will be pulled
low when right combination of inputs are
high…
CMOS gates are naturally inverting

MicroLab, VLSI-5 (2/34)

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 Complementary logic
Now you know what the “C”
in CMOS stands for!
We want complementary pullup and pulldown
logic, i.e., the pulldown should be “on” when
the pullup is “off” and vice versa.
pullup pulldown F(A1,…,An)
on off driven “1”
off on driven “0”
on on driven “X”
off off no connection

Since there’s plenty of capacitance on the output

node, when the output becomes disconnected it
“remembers” its previous voltage -- at least for a
while. The “memory” is the load capacitor’s charge.
Leakage currents will cause eventual decay of the
charge (that’s why DRAMs need to be refreshed!).

“No connection” is also useful for constructing

tristate drivers! In this case, we call this state
“Z” which is short for “high-
“high-Z” which is short for
“high impedance” which is how engineers say
“no connection”. Isn’t jargon wonderful?

MicroLab, VLSI-5 (3/34)

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 CMOS complements
What a nice Thanks. It runs
VOH you have... in the family...

pulldown pullup
nfet block pfet block

conducts when VGS is high conducts when VGS is low

A
A B
B

conducts when A is high conducts when A is low

and B is high: A.B or B is low: A+B = A.B

A
A B
B

conducts when A is high conducts when A is low

or B is high: A+B and B is low: A.B = A+B

MicroLab, VLSI-5 (4/34)

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 Development of CMOS gates /1

Example: CMOS NAND gate F = A*B

A
B 0 1
Step 1: development of nfet 0 1 1
block. Logic mini-
mini-
mization of “0” in 1 1 0
Karnaugh diagram

F=A*B

MicroLab, VLSI-5 (5/34)

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 Development of CMOS gates /2

A
B 0 1
Step 2: development of pfet 0 1 1
block. Logic mini-
mini-
mization of “1” in 1 1 0
Karnaugh diagram

F=A+B

A B

MicroLab, VLSI-5 (6/34)

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 Development of CMOS gates /2

A
B 0 1
Step 3: put nfet and pfet 0 1 1
block together
1 1 0

F=A*B

MicroLab, VLSI-5 (7/34)

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 NAND & NOR
2-input NAND. When output is low,
two nfets are in series. So to keep
output fall time equivalent to that
of an inverter, the nfets have to be
twice as wide. Pfet widths can be
A same as those in the inverter (but
remember there were already 2x nfet
widths!). Can be extended to large
B fan-
fan-in but practical limit is 4 inputs.
Why?

2-input NOR. When output is high,

B two pfets are in series. So to keep
output rise time equivalent to that
of an inverter, the pfets have to be
twice as wide. Nfet widths can be
same as those in the inverter. Can
be extended to large fan-
fan-in but
A practical limit is 4 inputs. NOR gates
are considered less good than NAND
gates. Why?

Pseudo-
Pseudo-NMOS NOR gates are
used to build high fan-
fan-in NOR
gates for PLA’s to save area
A1 … An
(at some cost in static power).

MicroLab, VLSI-5 (8/34)

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 Layout of simple gates
VDD p-type substrate

n-type well

metal/pdiff
metal/pdiff
contact
with detail
removed Wp

Lp

IN OUT

Wn

Ln contact
from metal
to ndiff
GND

metal2 metal poly n+ diff p+ diff

MicroLab, VLSI-5 (9/34)

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 Layout Rules #1

Š layout rules are the common language between

design and process engineers
Š conservative rules absorb process disturbances and
variations
Š layout rules must be respected by the designer
Š layout rules reflect the limits of a process, they
describe:
Š minimal distance, overlap
Š minimal width (e.x. channel length, λ)
Š layout readability is improved using colours:
metal blue
polysilicium red
n-diffusion green
p-diffusion yellow
n-well brown
contact, via black

MicroLab, VLSI-5 (10/34)

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 Layout Rules #2

symbol and mask layout of a CMOS inverter

n-well contact (n-
(n-diff)

bulk contact (p-

(p-diff)

MicroLab, VLSI-5 (11/34)

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 Stick Diagram

Š stick diagrams are technology independent

Š no layout rules need to be known
Š mask layout may be generated automatically

MicroLab, VLSI-5 (12/34)

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 NAND & NOR ((again
again))
again

MicroLab, VLSI-5 (13/34)

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 Fan--In CMOS Gates
Large Fan

CMOS gates with large fan-

fan-in suffer from:
Š body effect
Š unsymmetrical delay
Š large delay
⇒ never use more than 4 or 5 fets in series
⇒ increment logic depth

&
&

& ≥1

&

MicroLab, VLSI-5 (14/34)

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 CMOS Gate Recipe

A
Step 1. Figure out pulldown
network that does what you
want, e.g., F = A*(B+C) B C

Step 2. Walk the hierarchy

replacing nfets with pfets,
pfets,
B
series subnets with parallel A
subnets, and parallel C
subnets with series subnets

Step 3. Combine pfet

B
pullup network from Step A
2 with nfet pulldown C
network from Step 1 to
form fully-
fully-complementary A
CMOS gate.
But isn’t it B C
hard to wire
it all up?

MicroLab, VLSI-5 (15/34)

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 Complex CMOS Gates /1

Š classical CMOS logic gates are always inverting

logic gates
Š complex CMOS logic gates are a mixture of AND
and OR structures with a final inversion

Example: F = A * B + C * D

Step 1: generation of nfet

A C
block (logic “0”)
B D
F=A*B+C*D

C D
Step 2: generation of pfet
block (logic “1”)
A B
F = (A + B) * (C + D)

MicroLab, VLSI-5 (16/34)

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 Complex CMOS Gates /2

Step 3: put everything C D

together. What
about the layout ?
A B

A C
where is this signal
B D
in the transistor schema ?

A & ≥1
B

C &

MicroLab, VLSI-5 (17/34)

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 Complex CMOS Gates Layout /1

Goal: compact layout. All complex gates may be

designed using a single row of nfets and a single
line of pfets,
pfets, thus adjacent drain/source diffusions
of fets are very close.
Euler rule:
Š generate an n-n-graph by replacing the nfet block with
vertices for nodes and edges for fets
Š generate a dual p-p-graph
Š find a sequence containing all edges in the n-
n-graph.
This sequence is called Euler n-path.
Š generate an Euler p-path with the same labelling as
the Euler n-path. If not possible start again.
Š the labelling sequence of the 2 Euler paths are the
gate sequence of the single row nfet/
nfet/pfet CMOS
gate.

MicroLab, VLSI-5 (18/34)

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 Complex CMOS Gates Layout /2
VDD

C D
N1

A B
F

A C
N2 N3
B D

VSS start
F
C
A

start

VDD N3 N1 N2 F

D
B
VSS
A -> B -> D -> C
MicroLab, VLSI-5 (19/34)

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 Complex CMOS Gates /3
C D

A B
F

A C A -> B -> D -> C

B D

A B D C
MicroLab, VLSI-5 (20/34)

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 Complex CMOS Gates /4

C
A
B

B C

MicroLab, VLSI-5 (21/34)

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 A Quiz! /1

MicroLab, VLSI-5 (22/34)

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 A Quiz! /2

Find the minimal transistor circuit (2 * 4 fets)

fets) and
the most compact layout using Eulers rule.

CD
00 01 11 10
AB
00 1 1 1 1
01 0 0 0 0
11 0 0 0 0
10 1 0 0 0

MicroLab, VLSI-5 (23/34)

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 Quiz : Solution

F=A*B+B*C*D

F = B * ( A + C * D) equation ready for p-

p-block

C VDD

start
VSS P1 N1 F

A
D
P2
start

D -> C -> A -> B

MicroLab, VLSI-5 (24/34)

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 Transmission Gates
S
CMOS nMOS

A B A B

S
S

If VA = VDD then current will flow from

A to B until VB = _____

If VA = 0 then current will flow from

B to A until VB = _____

Assuming S and -S are complementary signals, the CMOS

transmission gate (TG) acts as a switch, controlled by S,
that has no inherent voltage drop (unlike a switch
constructed from a single nfet or pfet which exhibits at
VT drop at one rail or the other).

MicroLab, VLSI-5 (25/34)

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 CMOS TG Electrical Model
S=VDD S=0

A B A B

S=0 S= VDD
switch is off switch is “on”

How on is “on”? Assume VA = VDD then

nfet = sat nfet = sat nfet = off
pfet = sat pfet = lin pfet = lin

VB
0V |VT,p| VDD-VT,n VDD

R
Req,p
eq,p Req,n
eq,n

Req,TG
eq,TG
Req,n
eq,n || Req,p
eq,p

VB
0V VDD-VT,n VDD
MicroLab, VLSI-5 (26/34)

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 TG Circuits: MUX

A
Y=A*S+B*S

B
Is this node
always the “output”
S of this gate?

inverter
not drawn

MicroLab, VLSI-5 (27/34)

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 TG Circuits: 4 to 1 MUX

Š multiplexers can easily be done with TG

Š never forget that TG are bi-
bi-directional
Š compact layout by combining identical gates

B
F
C

S1
S2
MicroLab, VLSI-5 (28/34)

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 Best XOR in Town
A ≥1&
A =1 F B F
B ≥1

12 transistors
A

A*B+A*B
B
Is this node
always the “output”
8 transistors of this gate?

A A*B+A*B

B Is this node
always the “output”
of this gate?

6 transistors
MicroLab, VLSI-5 (29/34)

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 TG Quiz

Find the function of the following 4 transistor circuit:

MicroLab, VLSI-5 (30/34)

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 TG Circuits: Problems

Š difficult to get compact layout

Š outputs behave like bi-
bi-directional signals
Š many TG in series provoke large delays

Uin Uout

R R R R R
Uin Uout
C C C C C

τ = 2.2 ⋅ (RC )2

MicroLab, VLSI-5 (31/34)

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 Coming Up...
Next topic…
Dynamic ((precharge
precharge/evaluate)
precharge/evaluate) logic circuits:
CMOS domino logic, NP domino logic, CVSL logic.
Charge sharing.

Readings for next time…

Weste:
‹ Sections 5.3 thru 5.3.4 and 5.4.6
‹ 5.3.9 thru 5.4.1

MicroLab, VLSI-5 (32/34)

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 VLSI--5
Exercises: VLSI #1

Ex vlsi5.1 (difficulty: easy): Design a CMOS gate that

implements the function
Out = (( A + B) ⋅C + D ⋅ E ) ⋅ F

Ex vlsi5.2 (difficulty: easy): What is the Boolean

equation of the following CMOS gate.
VDD

A
B
Z

GND

MicroLab, VLSI-5 (33/34)

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 VLSI--5
Exercises: VLSI #2

Weste pp371: 5.9ex7 (difficulty: easy): Design a pass

transistor network that implements the sum
function for an adder
S = A ⋅B ⋅ C + A ⋅B ⋅C + A ⋅B ⋅ C + A ⋅B ⋅C

MicroLab, VLSI-5 (34/34)

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