ECE204/EEE204

Electrical Circuits II Laboratory

Experiment#02
Verification of KVL and KCL in AC Circuits
KCL(Kirchhoff's Current Law)
• the sum of currents that enter a junction is equal to the
sum of currents that leave the junction
• The sum of all currents that enter an electrical circuit
junction is 0. The currents enter the junction have
positive sign and the currents that leave the junction
have a negative sign. Therefore,
KVL(Kirchhoff's Voltage Law)
• The sum of all voltages or potential differences
in an electrical circuit loop is 0
KVL verification circuit
Procedures
• Construct the circuit in PSPICE as shown in
figure for KVL verification
• Determine the voltage Vs, VR, VL, and VC and the
current I from the schematics
• Sum up all the three voltages VR, VL, and VC
• Then verify,
Vs = VR+ VL+ VC
KCL verification circuit
Procedures
• Construct the circuit in PSPICE as shown in
figure for KCL verification
• Determine the currents IR1, IR2 and IR3 from
the schematics
• Sum up the branch currents IR2 and IR3
• Then verify,
IR1 = IR2 + IR3