AHB Protocol

Yadu Krishnan S
 AMBA : Advanced Microcontroller Bus Architecture

• Collection of on-chip bus protocol specifications

• Open standard on-chip interconnect specification developed by ARM
• Used as the on chip bus in ARM based SoC designs

Following are the main AMBA Protocols :

1. Advanced Peripheral Bus (APB)
2. Advanced System Bus (ASB)
3. Advanced High performance Bus (AHB)
4. Advanced eXtensible Interface (AXI)
5. AXI Coherency Extensions (ACE)
6. Coherent Hub Interface (CHI)
 Advanced Peripheral Bus (APB)

• Low-cost, simple interface that is optimized for minimal power consumption and reduced interface
complexity
• It is used to connect low-bandwidth peripherals. Mostly, used to connect the external peripheral to
the SOC
• It is connected to the system bus via a bridge
• It can also interface with AHB and AXI protocols using the bridges in between
Block Diagram
APB signals
Signal Source Description

PCLK Clock Source Clock. The rising edge of PCLK times all transfers on the APB.

System bus Reset. The APB reset signal is active LOW. This signal is normally
PRESETn
equivalent connected directly to the system bus reset signal.
Address. This is the APB address bus. It can be up to 32 bits wide and is
PADDR APB Bridge
driven by the peripheral bus bridge unit.
Protection type. This signal indicates the normal, privileged, or secure
PPROT APB Bridge protection level of the transaction and whether the transaction is a data
access or an instruction access.
Select. The APB bridge unit generates this signal to each peripheral bus
PSELx APB Bridge slave. It indicates that the slave device is selected and that a data
transfer is required. There is a PSELx signal for each slave.
Enable. This signal indicates the second and subsequent cycles of an
PENABLE APB Bridge
APB transfer.
Signal Source Description

Direction. This signal indicates an APB write access when HIGH and an
PWRITE APB Bridge
APB read access when LOW..

Write data. This bus is driven by the peripheral bus bridge unit during
PWDATA APB Bridge
write cycles when PWRITE is HIGH. This bus can be up to 32 bits wide.

Write strobes. This signal indicates which byte lanes to update during a
PSTRB APB Bridge write transfer. There is one write strobe for each eight bits of the write data
bus. Write strobes must not be active during a read transfer.

PREADY Slave interface Ready. The slave uses this signal to extend an APB transfer.

Read Data. The selected slave drives this bus during read cycles when
PRDATA Slave interface
PWRITE is LOW. This bus can be up to 32-bits wide.
This signal indicates a transfer failure. APB peripherals are not required to
support the PSLVERR pin. This is true for both existing and new APB
PSLVERR Slave interface
peripheral designs. Where a peripheral does not include this pin then the
appropriate input to the APB bridge is tied LOW.
 APB
Write
Without
Wait
State
APB Write
with Wait
State
(PREADY)
APB Read
without
Wait
State
APB Read
with Wait
State
(PREADY)
 Error
Response
(PSLVERR)
Operating States
Operating
States
• IDLE :  This is the default state of APB.
• SETUP : When transfer is required, PSELx is
asserted then the bus moves in setup state.
Bus only remains in SETUP for only one clock
cycle and always moves to ACCESS state on
next rising edge of clock. So, the slave must be
able to sample the Address and control
information in the SETUP cycle itself.
• ACCESS :  PENABLE is asseted to enter into the
ACCESS state. The PADDR, PWRITE, PSELx and
PWDATA signals must remain stable during
ACCESS state.
Thank you