Introduction to Sequential

Design
Types of Logic Circuits
 Logic circuits can be:
 Combinational Logic Circuits-outputs
depend only on current inputs

 Sequential Logic Circuits-outputs

depends not only on current inputs but
also on the past sequence of inputs
Sequential Circuit Models
 Combinational Logic Delay
Longest delay

A
5ns
B
5ns
5ns

Y
5ns
5ns D
C

Shortest delay

Longest timing delay = 5ns+5ns+5ns+5ns = 20ns

Shortest timing delay = 5ns

We will use the longest delay to represent the combinational logic (CL) delay, tcl
 Combinational Logic (CL)
Cloud Model

A
5ns
5ns
B

5ns CL
C Y
5ns
D
5ns E tcl

Tcl=20ns
Tcl=20ns
Memory
Memory
 We will add memory (or
registers) to our logic circuits.
This will allow us to design
sequential circuits.
Registers
 We will represent registers with the
following block diagram

ns R ps
E
G

clock
reset

Clock and reset are control signals

Ns and ps are data signals
Sequential Systems

Block Diagrams
 Sequential Systems
General Block Diagram
Next Present
State State
Output Vector
Input Vector CL
CL
ns R ps
E H
X F G Y

Clock
clock
reset Feedback
Reset Path

CL= Combinational Logic Cloud

Reg= D Registers
 Sequential Systems
General Block Diagram
Next Present
State State
Output Vector
Input Vector CL
CL
ns R ps
E H
X F G Y

Clock
clock
reset Feedback
Reset Path

X is the input data vector

Y is the output data vector
 Sequential Systems
Block Diagram
Next Present
State State
Output Vector
Input Vector CL
CL
ns R ps
E H
X F G Y

Clock
clock
reset Feedback
Reset Path

Ns is the next state data vector

Ps is the present state data vector
 Sequential Systems
Block Diagram
Next Present
State State
Output Vector
Input Vector CL
CL
ns R ps
E H
X F G Y

Clock
clock
reset Feedback
Reset Path

Notice we have a feedback path which

combines the ps data vector with the
input vector to generate a new ns data
vector.
 Sequential Systems
Block Diagram
Next Present
State State
Output Vector
Input Vector CL
CL
ns R ps
E H
X F G Y

Clock
clock
reset Feedback
Reset Path
Mathematically, we say
ns  F  X , ps 
Or, ns is a function F of X and ps
Y  H  ps  and Y is a function H of ps.
 F Logic Example Register

Circuit Schematic

X input ns ps
H Logic
(buffer)
CL CL
ns R ps
E H
X F G Y

Block Diagram
clock
reset
 F Logic Example Register

Circuit Schematic

X input ns ps
H Logic
(buffer)

State Equations

ns  J ps  K ps
Y  ps
Finite State Machine (FSM)

General Models
 Moore FSM
General Block Diagram
Next Present
State State
Output Vector
Input Vector CL
CL
ns R ps
E H
X F G Y

Clock
clock
reset Feedback
Reset Path

CL= Combinational Logic Cloud

Reg= D Registers
 Moore FSM
State Equations
Next Present
State State
Output Vector
Input Vector CL
CL
ns R ps
E H
X F G Y

Clock
clock
reset Feedback
Reset Path
State Equations
ns  F  X , ps 
Y  H  ps 
 Mealy FSM
Block Diagram and State Equations
Next Present
State State

CL CL
Input Vector Output Vector
ns R ps
E H
X F G Y

clock
reset
Feedback
ns  F  X , ps  Path

Y  H  X , ps 
Output Y is also a function
of input X
 Mealy-Moore FSM
Block Diagram and State Equations

Next State Present State

CL
Y1
Input Vector H1
CL
ns R
ps
E
X
F G Mealy Outputs
CL
Y2
H2
clock
reset

Moore Outputs
ns  F  X , ps 
Y1  H1  X , ps  Y2  H 2  ps 
State Diagrams
 State Bubble

State
Name [Conditional]
[Value]

(transition)
Output
 State Bubble Example
upn

Conditional
Transition
Unconditional
Transition
S0 upn
00

Y=0

State name = S0
State value = 00 We leave this state if upn=1,
We remain in this state if upn=0
Y = 0 for this state
Memory Devices
Memory Devices
 Data Latch (D-latch)
 Flip-flops (edge triggered)
 D-FF, D Register
 JK-FF
 T-FF
 D-FF Positive Edge Triggered
Block Diagram

Pre
Symbol
D SET Qn+1
4 inputs: D,Clk,Pre,Rst
D Q
Clk One output: Q
Q
D = Data Input
CLR

Rst
Clk = Clock Input
Pre = Preset Input
Rst = Reset Input
 D-FF Truth Table
Pre
Symbol
Qn+1 Truth Table
D D
SET
Q
Clk
D Clk Pre Rst Qn 1
CLR
Q d d 1 0 0
d d 0 1 1
Rst
d 0 1 1 Qn
d 1 1 1 Qn
Equation (rising clock) 0  1 1 0
1  1 1 1
Qn 1  Dn
 D-FF Truth Table
Pre
Symbol
Qn+1 Truth Table
D D
SET
Q
Clk
D Clk Pre Rst Qn 1
CLR
Q d d 1 0 0
d d 0 1 1
Rst
d 0 1 1 Qn
d 1 1 1 Qn
Equation (rising clock) 0  1 1 0
1  1 1 1
Qn 1  Dn
Pre= Preset Input (active low)
Rst = Reset Input (active low)
Highest priority
 D-FF Truth Table
Pre
Symbol
Qn+1 Truth Table
D D
SET
Q
Clk
D Clk Pre Rst Qn 1
CLR
Q d d 1 0 0
d d 0 1 1
Rst
d 0 1 1 Qn
d 1 1 1 Qn
Equation (rising clock) 0  1 1 0
1  1 1 1
Qn 1  Dn
D = Data Input
Clk = Clock input
Qn = Register Output
FSM Examples
 Example– 2-bit Up Counter
 State Diagram Reset

S0
Clock is implied
Y=0

s3 S1

Y=3 Y=1

S2

Y=2
Example – 2-bit Up Counter
 State Table State Value Assignment
Let S0 = 00
ps ns y
S1 = 01
S0 S1 0
S2 = 10
S1 S2 1
S3 = 11
S2 S3 2
S3 S0 3
Output
Vector
Let S0 = reset state
Example – 2-bit Up Counter
 Truth Table

ps1 ps0 ns1 ns0 y1 y0

0 0 0 1 0 0
0 1 1 0 0 1
1 0 1 1 1 0
1 1 0 0 1 1
Example – 2-bit Up Counter
 Excitation
Equations
ns1  ps1  ps 0
ns 0  ps 0
Y1  ps1
Y0  ps 0
 Moore FSM
Next Present
State State
Output Vector
Input Vector CL
CL
ns R ps
E H
X F G Y

Clock
clock
reset Feedback
Reset Path
State Equations
ns  F  X , ps 
Y  H  ps 
 Reg Block
Logic Diagram

F Logic
Y Vector

H Logic

No X Vector in this Example

No H Logic needed
Logic Diagram
 Application

Flash Animation
 Example 3– 2-bit Down Counter
 State Diagram Reset

S0
Clock is implied
Y=0

s3 S1

Y=3 Y=1

S2

Y=2
Example – 2-bit Down Counter
 State Table
Let S0 = 00
ps ns y
S1 = 01
S0 S3 0
S2 = 10
S3 S2 3
S3 = 11
S2 S1 2
S1 S0 1

Let S0 = reset state

Example – 2-bit Down Counter
 Truth Table

ps1 ps0 ns1 ns0 y1 y0

0 0 1 1 0 0
0 1 0 0 0 1
1 0 0 1 1 0
1 1 1 0 1 1
Example – 2-bit Down Counter
 Excitation
Equations

ns1  ps1  ps 0
ns 0  ps 0
Y1  ps1
Y0  ps 0
 Recall Moore FSM
Next Present
State State
Output Vector
Input Vector CL
CL
ns R ps
E H
X F G Y

Clock
clock
reset Feedback
Reset Path
State Equations
ns  F  X , ps 
Y  H  ps 
 Reg Block
Logic Diagram

F Logic
Y Vector

H Logic

No X Vector in this Example

Logic Diagram
Example 4 –
2-bit Up/Down Counter

 State Diagram Reset

upn S0
upn

upn upn
s3 S1
upn
upn

upn upn
S2
Example –
2-bit Up/Down Counter

 State Diagram Reset

upn S0

upn
s3 S1

S2

Shorthand Notation
Example – 2-bit Up/Down Counter

 State Table

ps ns ns y
upn upn Let S0 = 00
S0 S1 S3 0 S1 = 01
S1 S2 S0 1 S2 = 10
S2 S3 S1 2 S3 = 11
S3 S0 S2 3

Let S0 = reset state

 Example –
 Truth Table
2-bit Up/Down Counter
upn ps1 ps0 ns1 ns0 y1 y0
0 0 0 0 1 0 0
0 0 1 1 0 0 1
0 1 0 1 1 1 0
0 1 1 0 0 1 1
1 0 0 1 1 0 0
1 0 1 0 0 0 1
1 1 0 0 1 1 0
1 1 1 1 0 1 1
Example – 2-bit Up/Down Counter

 Excitation
Equations

ns1  ps1  ps 0  upn

ns 0  ps 0
Y1  ps1
Y0  ps 0
 Recall Moore FSM
Next Present
State State
Output Vector
Input Vector CL
CL
ns R ps
E H
X F G Y

Clock
clock
reset Feedback
Reset Path
State Equations
ns  F  X , ps 
Y  H  ps 
 Logic Diagram Reg Block

X Vector

F Logic
Y Vector

H Logic
Logic Diagram
Example 5– 3-bit Arbitrary Counter

 Design a 3-bit arbitrary counter that will

count in the following sequence
3,2,3,1,2,3
If a state is not used reset it to state zero.

• How may states do we have?

• How many registers do we need?
• How many bits do we need for Y?
Example 5– 3-bit Arbitrary Counter
 State Diagram

S7
S6 Reset

Y=0 S0
S5
Y=3
s4 S1

Y=2 Y=2

s3 S2

Y=1 Y=3
 Example – Arbitrary 3-bit Counter
 State Table Assign State Values
Let S0 = 000
ps ns y
S0 S1 3 S1 = 001
S1 S2 2 S2 = 010
S2 S3 3 S3 = 011
S3 S4 1 S4 = 100
S5 = 101
S4 S0 2
S6 = 110
S5 S0 0
S7 = 111
S6 S0 0
S7 S0 0 Let S0 = reset state
Develop Truth Table

Ps2 Ps1 Ps0 ns2 ns0 ns1 Y Y1 Y0

0 0 0 0 0 1 3 1 1
0 0 1 0 1 0 2 1 0
0 1 0 0 1 1 3 1 1
0 1 1 1 0 0 1 0 1
1 0 0 0 0 0 2 1 0
1 0 1 0 0 0 0 0 0
1 1 0 0 0 0 0 0 0
1 1 1 0 0 0 0 0 0
 Example – 2-bit Arbitrary Counter
 Develop Excitation Equations -- F Logic

ns 2  ps 2 ps1 ps 0
ns1  ps 2  ps1  ps 0 
ns 0  ps 2 ps 0
Develop Excitation Equations for Y
00 01 11 10

Y1 0 1 1 1

1 1

Y0
 Example – 2-bit Arbitrary Counter
 Excitation Equations -- H Logic

 
y1  ps 2 ps1  ps 0  ps1 ps 0


y0  ps 2 ps1  ps 0 
 Recall Moore FSM
Next Present
State State
Output Vector
Input Vector CL
CL
ns R ps
E H
X F G Y

Clock
clock
reset Feedback
Reset Path
State Equations
ns  F  X , ps 
Y  H  ps 
Logic Circuit

R H
E
G
F
Logic Circuit
Simulation
 Example 5– 2-bit Up/Down Counter with Active Low Enable and
Synchronous RESET (SRESET)

 State Diagram en srn

srn Resetn

Clock is implied S0
upn en srn upn en srn

upnen srn upnen srn

s3 srn S1

upnen srn en srn

en srn upnen srn

upn en srn

upn en srn S2

en srn
 Example – 2-bit Up/Down Counter with
Enable and SRESET

 Functional Table

srn en upn Function

0 d d Synchronous Reset (sreset)

1 1 d Hold
1 0 0 Count Up
1 0 1 Count Down

Highest Level of Priority Lowest Level of Priority

State Table

Srn En up ns
n
0 d d S0
1 1 d ps
1 0 0 ps+1
1 0 1 ps -1
 Truth Table (5 variables!!)
Srn En Upn Ps1 Ps0 Ns0 Ns1 # of Rows
0 d d d d 0 0 16
1 1 d Ps1 Ps0 Ps1 Ps0 8
1 0 0 0 0 0 1 1
1 0 0 0 1 1 0 1
1 0 0 1 0 1 1 1
1 0 0 1 1 0 0 1
1 0 1 0 0 1 1 1
1 0 1 0 1 0 0 1
1 0 1 1 0 0 1 1
1 0 1 1 1 1 1 1
32

Although, we could design this circuit directly from the truth table
we will use design partitioning.
 Moore FSM Architecture
Next Present
State State
Output Vector
Input Vector CL
CL
ns R ps
E H
X F G Y

clock
reset Feedback
Path
ns  F  X , ps 
Y  H  ps 
 Partitioned Design
ps
A
3 CL
UP/Down A ns R
Logic 2 E H
Upn A MUX Y
G Y
"0" 1
Mux ps
A
"0" 0
S0
S1

srn srn
We have
en en Srn En ns

0 d S0
clock
1 1 PS
reset

1 0 Count
Note, with the partitioned design we can “reuse” already designed submodules
to create the “new” design.
Top Level Block Diagram
 UP/Down Logic

Logic Circuit
Symbol
 Register Block

Symbol

Logic Circuit
 2 Bit 4x1 Mux
Circuit

Symbol
 1-bit 4x1 Mux
Logic Circuit

Symbol
 1-bit 2x1 Mux
Logic Circuit

Symbol
Top Level Block Diagram
Simulation
 Example 6 – FSM Controller
State Diagram se
t=0
re

S0

T T
S3 S1
T
1
3

S2 T

2
 Truth Table for NS
Truth Table
0
et=
s
re

S0

T T
S3 S1
T
1
3

S2 T

2
Kmaps for NS1 and NS0 NS1

ns1  T ps 0  T ps1  ps1 ps 0

NS0

ns0  T ps1  T ps 0  ps1 ps 0

Truth Table and Equations for Y
Truth Table

Recall, Moore FSM, so Y will

Not be a function of T

By Inspection

Y1  PS1 ; Y0  PS0
Logic Circuit

F R H
E
G
Simulation
Memory Devices
Flip-Flops
 D-FF Truth Table
Qn follows D on Rising Edge of CLK
Pre
Symbol
Qn+1 Truth Table
D D
SET
Q
Clk
D Clk Pre Rst Qn 1
CLR
Q d d 1 0 0
d d 0 1 1
Rst
d 0 1 1 Qn
d 1 1 1 Qn
Equation (rising clock) 0  1 1 0
1  1 1 1
Qn 1  Dn
D = Data Input
Clk = Clock input
Qn = Register Output
 T-FF (Toggle)
Changes state on every tick of CLK
Pre
Symbol

Qn+1
T Clk Pre Rst Qn 1
T T
SET
Q D d 1 0 0
Clk
D d 0 1 1
CL
R
Q d 0 1 1 Qn
d 1 1 1 Qn
Rst
0  1 1 Qn

Equation (rising clock)

1  1 1 Qn
Truth Table
Qn 1  TQn  T Qn
 SR-FF
Set =>Qn=1
Reset=>Qn=0
Symbol
Pre S R Clk Pre Rst Qn 1
d d d 1 0 0
Qn+1
S S
SET
Q d d d 0 1 1
Clk
d d 0 1 1 Qn
R Qn
R CLR
Q d d 1 1 1
0 0  1 1 Qn
Rst
0 1  1 1 0
1 0 1 1 1

1 1 1 1 ???
Equation (rising clock) 
Qn 1  S RQn  S R Truth Table
 JK-FF

Symbol
Pre J K Clk Pre Rst Qn 1
Qn+1
d d d 1 0 0
J J
SET
Q d d d 0 1 1
Clk
d d 0 1 1 Qn
K Qn
K CLR
Q d d 1 1 1

Rst
0 0  1 1 Qn
0 1  1 1 0
1 0  1 1 1

Equation (rising clock) 1 1  1 1 Qn

Truth Table
Qn 1  J Qn  KQn
 Example: Design a JK-FF using
only Logic and a D-FF
Symbol
Pre J K Clk Pre Rst Qn 1
Qn+1
d d d 1 0 0
J J
SET
Q d d d 0 1 1
Clk
d d 0 1 1 Qn
K Qn
K CLR
Q d d 1 1 1

Rst
0 0  1 1 Qn
0 1  1 1 0
1 0  1 1 1
1 1  1 1 Qn

Truth Table
 Example
State Diagram State Table

Reset J

J S0 S1 K
0 1

Let s0=0 and s1=1

 JK-FF

Truth Table Logic Equations

ns  J ps  K ps
Y  ps
 Recall Moore FSM
State Equations
Next Present
State State
Output Vector
Input Vector CL
CL
ns R ps
E H
X F G Y

Clock
clock
reset Feedback
Reset Path
State Equations
ns  F  X , ps 
Y  H  ps 
 F Logic JK Example D-Register

Circuit Schematic

X input ns ps
H Logic
(buffer)
CL CL
ns R ps
E H
X F G Y

Block Diagram
clock
reset
 JK Example

Circuit Schematic Simulation

Latches
 D-Latch Block Diagram
Symbol Pre

Qn+1
4 inputs: D,E,Pre,Rst
D SET
D Q
One output: Q
E E

CLR
Q

Rst
D = Data Input
E = Enable Input
Pre = Preset Input
Rst = Reset Input
 D-Latch
Truth Table
Symbol Pre
Truth Table

D SET Qn+1 D E Pre Rst Qn 1

D Q
E d d 1 0 0
E
d d 0 1 1
Q Qn
CLR
d 0 1 1

Rst 0 1 1 1 0
1 1 1 1 1
 D-Latch
State Equations
Symbol Pre
Truth Table

D SET Qn+1 D E Pre Rst Qn 1

D Q
E d d 1 0 0
E
d d 0 1 1
Q Qn
CLR
d 0 1 1

Rst 0 1 1 1 0
1 1 1 1 1

Equation (level clock)

Qn 1  EQn  EDn
 SR-Latch
State Equations
Symbol Pre
Truth Table

S SET Qn+1 S R Pre Rst Qn 1

S Q
d d 1 0 0
R R
d d 0 1 1
CLR
Q 0 0 1 1 Qn
0 1 1 1 0
Rst
1 0 1 1 1
1 1 1 1 ???
Equation (level clock)

Qn 1  S RQn  S R
Example

T-FF

D-FF

D-Latch
Simulation
Modular Sequential Logic
Shift Registers
 Logic Design which manipulates the
bit position of binary data by
shifting it to the left or right.
 Major application
 Serial Data to Parallel Data converters
Example
 Design a three-bit shift register with
the following functions

S1 S0 Function

0 0 Synchronous Reset (sreset)

0 1 Shift Right
1 0 Shift Left
1 1 No Shift
Partitioned Design

ps
A
3
Shift Left A ns R
2 E
A MUX Y
G
Y
1
Mux ps
Shift A
Right 0
"0" S1
S0

S1

S0

clock

reset
 No Shift Equations and Circuit

ns 2  ps 2
ns1  ps1
ns 0  ps 0
 Shift Left Equations and Circuit

ns 2  ps1
ns1  ps 0
ns 0  ps 2 Shift
ps ns
Left
 Shift Right Equations and Circuit

ns 2  ps 0
ns1  ps 2
ns 0  ps1
ps
Shift ns
Right
Synchronous Reset Module

ns 2  0
ns1  0
ns 0  0
Registers
Total Design