SEQUENTIAL LOGIC CIRCUIT

• SEQUENTIAL LOGIC CIRCUITS are circuits that depend on present

inputs and past outputs
• It has memory
TYPES OF SEQUENTIAL LOGIC
CIRCUITS
• 1.SYNCHRONOUS SEQUENTIAL CIRCUITS
• 2.ASYNCHRONOUS SEQUENTIAL CIRCUITS
COMPARE ASYNCHRONOUS AND
SYNCHRONOUS LOGIC CIRCUITS
SYNCHRONOUS ASYNCHRONOUS
1.Controlled by clock signal Not controlled by clock signal
2.Clock decides the speed faster
3.Output changes with input with clock Output changes with change in input
4.Easier to design Difficult to design
5.Memory elements are clocked flipflops Memory elements are unclocked flipflops6.
6.Time variable is discrete Time variable is continous

In input and output signals are defined at every value

7. Inputs and outputs are considered at discrete time instants. of time.
FLIP FLOP

S R LATCH
Types of flip flops
1.S R FLIP FLOP
2.D FLIP FLOP
3.JK FLIP FLOP
4.JK MASTER SLAVE FLIP FLOP
5.T (TOGGLE) FLIP FLOP
SR FLIP FLOP
Set Reset flip flop
Three inputs S,R and CLK
Circuit responds only when CLK is active
Has two states SET and reset

S R Q N+1 STATE
0 0 INVALID NOT USED
0 1 0 RESET
1 0 1 SET
1 1 QN PREVIOUS
STATE
SR flipflop with preset and clear
• PRESET and
CLEAR :Asynchronous inputs
• Active Low Inputs
• When PRESET=0;Q=1
• When CLEAR=0;Q=0
• When PRESET=CLEAR=1 ;Normal
operation
D FLIP FLOP

D
J K FLIP FLOP J K Q N+1 STATE
0 0 QN PREVIOU
S STATE

0 1 0 RESET
1
•1 0 1 SET
1 1 QN TOGGLE

• 1.Has 3 inputs J and K and CLK

• 2.Eliminates invalid condition in
SR flip flop
• 3.Dis advantage of JK flipflop
Race Around Condition
RACE AROUND CONDITION

• In JK flipflop when J=K=1and CLK=1;O/P toggles between 0 and 1.This

is called race around condition.
• Methods to eliminate Race around condition
1.use clock pulse with TON <Propagation delay of ckt
2.Use edge triggering flip flop
3. Use master slave flip flop
 J K Q N+1 STATE
0 0 QN PREVIO
US
MASTER SLAVE J K FLIP 0FLOP
1 0
STATE
RESET
1 0 1 SET
1 1 QN

CLK
CLK
• In J K Master-Slave Flip-Flop two JK flip-flops are connected together in
• One acts as the “master” and the other as a “slave”.
• The output from the master flip flop is connected to the inputs of the
slave flip flop
• Original clock signal is given to the master and inverted one to the slave.
• When CLK is HIGH master is enabled and slave is disabled
• When CLK is LOW master is disabled and slave is enabled
• When J=K=1 and CLK=1 O/P of master toggles;but it doesnot reach the
slave.
• When CLK=0 ;slave is enabled andO/P of master is transmitted to slave .
• Thus Race around condition is eliminated
 TOGGLE FLIP FLOP

The toggle, or T, flip-flop is obtained by connecting J and K inputs of JK FLIP FLOP

If the toggle input is HIGH, output toggles when the clock signal is applied.
If the toggle input is LOW, OUTPUT is the previous state..