CH 3 - Processor Organization and Architecture

Chapter 3
Processor Organization and

Architecture
CE – SE – Digital Logic & Computer Organization

and Architecture
Prof. Kalyani N Pampattiwar
Asst. Prof.
Dept. of Computer Engineering,
SIES Graduate School of Technology
1
What is a Multiplexer (MUX)?
A MUX is a digital switch that Multiplexer
has multiple inputs (sources) Block Diagram
and a single output
(destination).
2N 1
The select lines determine Inputs Output
MUX
(destination)
which input is connected to the (sources)
output.
MUX Types N
 2-to-1 (1 select line)
Select
 4-to-1 (2 select lines) Lines
 8-to-1 (3 select lines)
2
Typical Application of a MUX
Multiple Sources Selector Single Destination
MP3 Player
Docking Station
D0
Laptop
D1
MUX
Sound Card Y
D2
D3
Surround Sound System
Digital B A Selected Source

Satellite
0 0 MP3
0 1 Laptop
1 0 Satellite
Digital
1 1 Cable TV
Cable TV
3
4-to-1 Multiplexer (MUX)
D0
D1
MUX
Y
D2
D3
B A
B A Y
0 0 D0
0 1 D1
1 0 D2
1 1 D3
4
4-to-1 Multiplexer Waveforms
D0
D1
Input
Data
D2
D3
A Select
Line
Output
Y Data
D0 D1 D2 D3 D0 D1 D2 D3 5
Medium Scale Integration MUX
4-to-1 MUX 8-to-1 MUX 16-to-1 MUX
Inputs Output (Y)

(and inverted output)
Select
Enable
6
What is a Demultiplexer (DEMUX)?
A DEMUX is a digital switch Demultiplexer
with a single input (source) and Block Diagram
a multiple outputs
(destinations).
1 2N
The select lines determine
DEMUX
Input Outputs
(source)
which output the input is (destinations)
connected to.
DEMUX Types N
 1-to-2 (1 select line) Select

 1-to-4 (2 select lines) Lines
7
Typical Application of a DEMUX
Single Source Selector Multiple Destinations
B/W Laser
Printer
Fax
Machine
D0
DEMUX
X D1
D2 Color Inkjet
Printer
D3
B A Selected Destination
0 0 B/W Laser Printer Pen
0 1 Fax Machine Plotter
1 0 Color Inkjet Printer

1 1 Pen Plotter
8
1-to-4 De-Multiplexer (DEMUX)
D0
DEMUX
D1
X
D2
D3
B A
B A D0 D1 D2 D3
0 0 X 0 0 0
0 1 0 X 0 0
1 0 0 0 X 0
1 1 0 0 0 X
9
1-to-4 De-Multiplexer Waveforms
Input
X Data
S0
Select
Line
S1
D0
D1
Output
Data
D2
D3
10
Medium Scale Integration DEMUX
1-to-4 DEMUX 1-to-8 DEMUX 16-to-1 MUX
Select
Outputs
(inverted)
Input
(inverted)
Note : Most Medium Scale Integrated (MSI) DEMUXs , like

the three shown, have outputs that are inverted. This is done
because it requires few logic gates to implement DEMUXs
with inverted outputs rather than no-inverted outputs. 11
Seeing Is NOT Always Believing
• Our lives are filled with
electronic signs that display the
time, temperature, or ball game
score. However, what we see is
not always what is really
brgprecision.com
happening.
• In fact for most displays, the electronic-scoreboard.com
individual display segments are
cycled through so that only one
display is on at any given time.
• The cycle speed is so fast that
the human eye perceives that all
segments are on. digicam-tech.com
nu-mediadisplays.com/signs/time-
displays.php
12
Simple Message: All Segments On
• The circuit to the right uses
four 7-segment displays to
display the word CIAO. In
this circuit all displays are
continuously illuminated,
each displaying one letter in
the word.
• Though this method works, it
is a VERY inefficient use of
power. To illuminate the
simple message CIAO in this
way, 18 segments must be
continuously on.
• Can you think of another way
to display this message that
would use less power?
13 13
Decoder
• A decoder which has an n bit binary input code and a one

activated output out of 2^n output code is called binary
decoder
• Definition: A decoder is a multiple input, multiple output
logic circuit which converts coded input into coded output,
where input and output codes are different. The input code
generally has fewer bits than the output code
14
2 line to 4 line decoder( 74139)
15
3 to 8 line decoder (IC 74138)
The 74LS138 is a 3-to-8 decoder with three chip select

inputs (two active LOW, one active HIGH)
16
3 to 8 line decoder : Truth Table
17
Minterms using OR Gates

Minterms using NOR Gates

Encoder
• Reverse operation of decoder

• Output is binary code
20
Octal to Binary Encoder
21
Priority Encoder
• It is an encoder circuit that includes the priority function.

• If two or more inputs are equal to 1 at the same time , the input
with highest priority will be taken first
22
Priority Encoder
23
Quiz Time
https://forms.office.com/Pages/ResponsePage.aspx?
id=NNxdQGDW5Ua1Lb_QvhVrtdmwybw-
nDBDt3faX8MQK6NUOEVEMVUyM00yRk5DQTFBUDdaUjJaSkhDTi4u
24
Difference between combinational and sequential circuit
Combinational circuits are defined as the time independent

circuits which do not depends upon previous inputs to generate
any output are termed as combinational circuits.
Sequential circuits are those which are dependent on clock

cycles and depends on present as well as past inputs to generate
any output.
25
Combinational Circuit
1. In this output depends only upon present

input.
2. Speed is fast.
3. It is designed easy.
4. There is no feedback between input and
output.
5. This is time independent.
6. Elementary building blocks: Logic gates
7. Used for arithmetic as well as boolean
operations.
8. Combinational circuits don’t have
capability to store any state.
9. As combinational circuits don’t have clock,
they don’t require triggering.
10. These circuits do not have any memory
element.
11. It is easy to use and handle.
Examples – Encoder, Decoder, Multiplexer,
Demultiplexer
26
Sequential Circuit
1. In this output depends upon present

as well as past input.
2. Speed is slow.
3. It is designed tough as compared to
combinational circuits.
4. There exists a feedback path
between input and output.
5. This is time dependent.
6. Elementary building blocks: Flip-flops
7. Mainly used for storing data.
8. Sequential circuits have capability to
store any state or to retain earlier
state.
9. As sequential circuits are clock
dependent they need triggering.
10. These circuits have memory element.
11. It is not easy to use and handle.
Examples – Flip-flops, Counters
27
Flip Flop
• A Flip Flop is a memory element that is capable of storing one bit
of information.
• If it store 0 Reset FF
1 Set FF
• A flip flop has two outputs as shown-
• A flip flop can maintain a binary state for an unlimited period of time as long
as- 1) Power is supplied to the circuit.
2)Or until it is directed by an input signal to switch states.
• A flip flop is also called as Bistable Multivibrator because it has two stable
states either 0 or 1.
28
One bit memory cell
Q=0, Q’=1 Reset FF

Q=1 , Q’=0 Set FF
29
conclusion of 1 bit memory cell
1. output of the flip flop are always complementary of each other

2. if Qn=0 then Qn’=1; condition is reset
Qn=1 then Qn’=0 condition is set
3. If Qn=0 then Qn’=1. this condition will remain as it is till we
can change Qn=1 .so so this device has capability to store 1 bit
information
30
Difference between latch and flip flop
1. Latch changes its output according to the changes in the

input
2. Flip flop changes its output only at particular instants of time
and not continuously( according to to clock pulse applied)
3. Latch is level triggered flip flop and flip flop is edge triggered
31
Types of Flip Flop
There are following 4 basic types of flip flops-
32
1. S-R FF
• SR flip flop is the simplest type of flip flops.
• It stands for Set Reset flip flop.
• It is a clocked flip flop.
Construction of SR Flip Flop-
There are following two methods for constructing a SR flip flop-
1. By using NOR latch

2. By using NAND latch
33
1. Construction of SR Flip Flop By Using NOR Latch-
This method of constructing SR Flip Flop uses-
• NOR latch
• Two AND gates
Logic Circuit-
The logic circuit for SR Flip Flop constructed using NOR latch is
as shown below-
34
2. Construction of SR Flip Flop By Using NAND Latch-
This method of constructing SR Flip Flop uses-
• NAND latch
• Two NAND gates
Logic Circuit-
The logic circuit for SR Flip Flop constructed using NAND

latch is as shown below-
35
Logic Symbol-
The logic symbol for SR Flip Flop is as shown below-
Truth Table- INPUTS OUTPUTS
The truth table for SR Flip S R

Qn Qn+1
Flop is as shown below- (Present State) (Next State)
0 0 0 0
0 0 1 1
0 1 0 0
0 1 1 0
1 0 0 1
1 0 1 1
1 1 0 Indeterminate
1 1 1 Indeterminate
36
The above truth table may be reduced as-
INPUTS OUTPUTS REMARKS
Qn Qn+1
S R States and Conditions
(Present State) (Next State)
0 0 X Qn Hold State condition S = R = 0
0 1 X 0 Reset state condition S = 0 , R = 1
1 0 X 1 Set state condition S = 1 , R = 0
Indeterminate state condition S = R =

1 1 X Indeterminate
1
• Qn is the binary state of FF before the occurrence of clock pulse known as

present state
• Qn+1 is the state of FF after the occurrence of clock pulse known as Next
state
37
Characteristic Equation of SR FF -
Draw a k map using the above truth table-
From here-
Qn+1 = ( SR + SR’ ) ( Qn + Q’n ) + Qn ( S’R’ + SR’ )

Qn+1 = S + QnR’
38
What is excitation table?
For a given combination of present state Qn and next state Qn+1,

excitation table tell the inputs required.
Excitation Table-
The excitation table of any flip flop is drawn using its truth table.
Qn Qn+1 S R
0 0 0 X
0 1 1 0
1 0 0 1
1 1 X 0
Excitation Table
39
2. JK Flip Flop( Jack and Kilby)
1. Construction of JK Flip Flop By Using SR Flip Flop Constructed
From NOR Latch-
This method of constructing JK Flip Flop uses-
• SR Flip Flop constructed from NOR latch
• Two other connections
Logic Circuit-
The logic circuit for JK Flip Flop constructed using SR Flip Flop
constructed from NOR latch is as shown below-
40
2. Construction of JK Flip Flop By Using SR Flip Flop Constructed
From NAND Latch-
This method of constructing JK Flip Flop uses-

• SR Flip Flop constructed from NAND latch
• Two other connections
Logic Circuit-
The logic circuit for JK Flip Flop constructed using SR Flip Flop
constructed from NAND latch is as shown below-
41
Logic Symbol-
The logic symbol for JK Flip Flop is as shown below-
INPUTS OUTPUTS
Qn Qn+1
J K
Truth Table- (Present State) (Next State)
0 0 0 0
The truth table for JK Flip
Flop is as shown below- 0 0 1 1
0 1 0 0
0 1 1 0
1 0 0 1
1 0 1 1
1 1 0 1
1 1 1 0
42
The above truth table may be reduced as-
INPUTS OUTPUTS REMARKS
Qn Qn+1
J K States and Conditions
(Present State) (Next State)
0 0 X Qn Hold State condition J = K = 0
0 1 X 0 Reset state condition J = 0 , K = 1
1 0 X 1 Set state condition J = 1 , K = 0
1 1 X Q’n Toggle state condition J = K = 1
43
Characteristic Equation-
Draw a k map using the above truth table-
From here-
Qn+1 = Q’n (JK + JK’) + Qn (J’K’ + JK’)
Qn+1 = Q’nJ + QnK’
44
Excitation Table-
45
• To avoid invalid condition of SR FF (S=R=1) JK FF is designed in
which input is feedback as a output
Race around condition in JK flip-flop:
• In JK flip flop as long as clock is high for the input conditions J&K
equals to the output changes or complements its output from 1–>0
and 0–>1.
• This is called toggling output or uncontrolled changing or racing
condition. Consider above J&K circuit diagram as long as clock is
high and J&K=11 then two upper and lower AND gates are only
triggered by the complementary outputs Q and Q(bar). I.e. in any
condition according to the propagation delay one gate will be
enabled and another gate is disabled.
• If upper gate is disabled then it sets the output and in the next lower
gate will be enabled which resets the flip flop output. 46
Steps to avoid racing condition in JK Flip flop:
• If the Clock On or High time is less than the propagation
delay of the flip flop then racing can be avoided. This is done
by using edge triggering rather than level triggering.
• If the flip flop is made to toggle over one clock period then
racing can be avoided. This introduced the concept of Master
Slave JK flip flop
47
SR Flip Flop Vs JK Flip Flop-
Both JK flip flop and SR flip flop are functionally same.

The only difference between them is-
• In JK flip flop, indeterminate state does not occur.
• In JK flip flop, instead of indeterminate state, the present state
toggles.
• In other words, the present state gets inverted when both the
inputs are 1.
48
3. D (Delay) Flip Flop
• Looking at SR FF truth table we realize that when both the

inputs are same, the output is either does not change or it
is unpredictable
• In many practical applications these input conditions are
not required
• These input conditions can be avoided by making them
complement of each other
• Modified clocked SR FF is known as D FF
49
Logic Symbol and Truth table
Excitation table Prof. Kalyani N Pampattiwar

50
4. T (Toggle) FF
51
• T FF is a modification of JK FF
• T FF is obtained from a JK FF by connecting both inputs J & K
• When T=0 (J=K=0) both AND gates are disabled and hence
there is no change in the output
• When T=1 ( J=K=1) we will get output as Qn’ i.e., output
toggles
52
CPU with system bus
53
Register Organization
The registers in processor perform two roles
1. User visible registers
- Enable assembly language programmer to minimize main
memory references by optimizing use of registers
2. Control and Status registers
- Used by CU to control the operation of processor and by
privileged, operating system programs to control the execution of
programs
There is no clean separation of registers between these two
categories.
54
1. User Visible Registers
User Visible
Registers
General Condition
Data Address
purpose codes
55
2. Control and Status Registers
Control and
Status
Registers
Memory
Program Instruction Memory Buffer
Address
Counter Register Register
Register
Carry
Equal
Overflow
Interrupt
Supervisor
56
Addressing Modes
• Needed to reference a large range of locations in main
memory
• Common addressing techniques are:
> Immediate Addressing Mode
> Direct Addressing Mode
> Indirect Addressing Mode
> Register Addressing Mode
> Register indirect Addressing Mode
> Displacement Addressing Mode
> Stack Addressing Mode

57
1. Immediate
• Operand value is present in instruction

• Used for constants
• Operand=A
• No memory reference needed
• 0 cycles
e.g. MOV BL,25H

MOV BX,2000H
58
2. Direct Addressing
• Address field contains effective address of operand

• EA=A
• E.g. MOV BL,[2000H]
• Used in accessing static data
• 1 Memory reference
• 2 cycles
59
3. Indirect Addressing
• Used for accessing series of locations

• EA=(A)
60
Brainstorming
1. Get data from location 5000

2. Get data from location starting from 5000 location
VOTING LINK
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61
4. Register Addressing
• Similar to direct addressing

• Only difference is that the address field refers to a register rather than MM
address
• EA=R
• e.g. MOV BL,CL
• MOV BX,CX
• 1 register reference, 1 cycle 62
5. Register Indirect
• Similar to indirect addressing

• Only difference is whether address field refers to memory lo memory
location or a register
• EA=(R )
• E.g. MOV, CL,{BX}
63
6. Displacement addressing
• Combination of Direct & register indirect addressing

• EA=A+(R )
• For accessing local variables
64
7 Stack Addressing
• Stack is a linear array locations

• Stack pointer is maintained in a register
• References to stack locations in memory are in fact register
indirect addresses
65
Question?
BL 2000
CL 3000
Add BL + 55
Store BL to 4000 location
Solution:
MOV BL,[2000H]
MOV CL,[3000H]
ADD BL,CL
ADD BL,55
MOV [4000H],BL
66
Instruction
• Computer perform task on the basis of instruction provided. A
instruction in computer comprises of groups called fields.
These field contains different information as for computers
every thing is in 0 and 1 so each field has different
significance on the basis of which a CPU decide what to
perform. The most common fields are:
 Operation field which specifies the operation to be performed

like addition.
 Address field which contain the location of operand, i.e.,
register or memory location.
 Mode field which specifies how operand is to be found.

A instruction is of various length depending upon the number of
addresses it contain. Generally CPU organization are of three
types on the basis of number of address fields:
1. Single Accumulator organization
operation is done involving a special register called accumulator
2. General register organization
multiple registers are used for the computation purpose
3. Stack organization
It work on stack basis operation due to which it does not contain
any address field

Instruction Interpretation and Sequencing
• Types of Instruction
1) Data Transfer Instruction

Copy information from one location to another either in the processors internal register
set or in the external main memory.
e.g. R1 X
R1 R2
X R1
2) Arithmetic Instructions
Perform operations on numerical data
e.g. R1 R2+R1
X R1+Y
3) Logical Instructions
Include Boolean and other non numerical operation
69
4) Program Control Instructions
Branch instructions which change the sequence in which programs are executed
e.g. Loop Conditional
JMP Unconditional
5) I/O Instruction
Which cause information to be transferred between the processor or its main memory
and external I/O devices
Add A & B without altering A & B

i.e., C=A + B
70
1. Zero Address Instructions

A stack based computer do not use address field in instruction.
To evaluate a expression first it is converted to revere Polish
Notation i.e. Post fix Notation.
Expression:
X = (A+B)*(C+D)
Postfixed : X = AB+CD+*
TOP means top of stack
M[X] is any memory location

PUSH A TOP = A
PUSH B TOP = B
ADD TOP = A+B
PUSH C TOP = C
PUSH D TOP = D
ADD TOP = C+D
TOP =
MUL
(C+D)*(A+B)
POP X M[X] = TOP

2. One Address Instructions
This use a implied ACCUMULATOR register for data
manipulation. One operand is in accumulator and other is in
register or memory location.Implied means that the CPU already
know that one operand is in accumulator so there is no need to
specify it.

2. One Address Instructions
Expression: X = (A+B)*(C+D)
AC is accumulator
M[ ] is any memory location
M[T] is temporary location

LOAD A AC = M[A]
AC = AC +
ADD B
M[B]
STORE T M[T] = AC
LOAD C AC = M[C]
AC = AC +
ADD D
M[D]
AC = AC *
MUL T
M[T]
STORE X M[X] = AC

3. Two Address Instructions
This is common in commercial computers. Here two address can

be specified in the instruction. Unlike earlier in one address
instruction the result was stored in accumulator here result can
be stored at different location rather than just accumulator, but
require more number of bit to represent address.

Here destination address can also contain operand.
R1, R2 are registers
M[] is any memory location

MOV R1, A R1 = M[A]
R1 = R1 +
ADD R1, B
M[B]
MOV R2, C R2 = C
ADD R2, D R2 = R2 + D
MUL R1, R2 R1 = R1 * R2
MOV X, R1 M[X] = R1

4. Three Address Instructions
This has three address field to specify a register or a memory

location. Program created are much short in size but number of
bits per instruction increase. These instructions make creation of
program much easier but it does not mean that program will run
much faster because now instruction only contain more
information but each micro operation (changing content of
register, loading address in address bus etc.) will be performed
in one cycle only.

R1, R2 are registers
M[ ] is any memory location

ADD R1, A, B R1 = M[A] + M[B]
ADD R2, C, D R2 = M[C] + M[D]
MUL X, R1, R2 M[X] = R1 * R2

Q1) Explain different instruction formats.
Q2) Explain Instruction cycle.

Instruction cycle

Data Flow Fetch Cycle

Data Flow Indirect Cycle

Data Flow Interrupt Cycle

Quiz Time
https://forms.gle/gbxzEjXa7z4AHxkbA
88
Thank You!!
89

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Chapter 3

Processor Organization and

CE – SE – Digital Logic & Computer Organization

Surround Sound System

Digital B A Selected Source

4-to-1 MUX 8-to-1 MUX 16-to-1 MUX

Inputs Output (Y)

 1-to-2 (1 select line) Select

Single Source Selector Multiple Destinations

1 0 Color Inkjet Printer

1-to-4 DEMUX 1-to-8 DEMUX 16-to-1 MUX

Note : Most Medium Scale Integrated (MSI) DEMUXs , like

• A decoder which has an n bit binary input code and a one

The 74LS138 is a 3-to-8 decoder with three chip select

Prof. Kalyani N Pampattiwar

Prof. Kalyani N Pampattiwar

• Reverse operation of decoder

• It is an encoder circuit that includes the priority function.

Combinational circuits are defined as the time independent

Sequential circuits are those which are dependent on clock

1. In this output depends only upon present

1. In this output depends upon present

Q=0, Q’=1 Reset FF

1. output of the flip flop are always complementary of each other

1. Latch changes its output according to the changes in the

Construction of SR Flip Flop-

There are following two methods for constructing a SR flip flop-

1. By using NOR latch

The logic circuit for SR Flip Flop constructed using NAND

Truth Table- INPUTS OUTPUTS

The truth table for SR Flip S R

Flop is as shown below- (Present State) (Next State)

0 0 X Qn Hold State condition S = R = 0

0 1 X 0 Reset state condition S = 0 , R = 1

1 0 X 1 Set state condition S = 1 , R = 0

Indeterminate state condition S = R =

• Qn is the binary state of FF before the occurrence of clock pulse known as

Draw a k map using the above truth table-

Qn+1 = ( SR + SR’ ) ( Qn + Q’n ) + Qn ( S’R’ + SR’ )

For a given combination of present state Qn and next state Qn+1,

This method of constructing JK Flip Flop uses-

0 0 X Qn Hold State condition J = K = 0

0 1 X 0 Reset state condition J = 0 , K = 1

1 0 X 1 Set state condition J = 1 , K = 0

1 1 X Q’n Toggle state condition J = K = 1

Draw a k map using the above truth table-

Qn+1 = Q’n (JK + JK’) + Qn (J’K’ + JK’)

Qn+1 = Q’nJ + QnK’

Both JK flip flop and SR flip flop are functionally same.

• Looking at SR FF truth table we realize that when both the

Excitation table Prof. Kalyani N Pampattiwar

> Direct Addressing Mode

> Indirect Addressing Mode

> Register Addressing Mode

> Register indirect Addressing Mode

> Displacement Addressing Mode

> Stack Addressing Mode

• Operand value is present in instruction

e.g. MOV BL,25H

• Address field contains effective address of operand

• Used for accessing series of locations

1. Get data from location 5000

• Similar to direct addressing