Saba institute of higher education

Faculty of Computer Science

Basic Computer
Architecture
Data Manipulation

Khalil Ahmad Faizi

1
Contents
● Computer Architecture (Review)
● Machine Language
● Program
● Execution
● Arithmetic/Logic Instructions
● Communicating with Other Devices
Other Architectures

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Computer Architecture
●
Central Processing Unit (CPU) or processor
– Arithmetic/Logic unit versus
– Control unit
– Registers
●
General Purpose Registers
●
Special Purpose Registers
● Bus
● Motherboard
● Memory
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 CPU and main memory connected via a
bus

Fig 5.1
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Instruction Codes
A process is controlled by a program
– A program is a set of instructions that specify
the operations, data, and the control sequence
– An instruction is stored in binary code
that specifies a sequence of micro-
operations
– Instruction codes together with data are stored
in memory (Stored Program Concept)

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Stored Program Concept
●
A program can be encoded as bit patterns and stored in
main memory. From there, the CPU can then extract
the instructions and execute them. In turn, the
program to be executed can be altered easily.

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Machine Language
●
Machine language: The set of all
instructions recognized by a machine
● Machine instruction: An instruction (or
command) encoded as a bit pattern recognizable
by the CPU

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Machine Instruction Types
●
Data Transfer: copy data from one location to
another
●
Arithmetic/Logic: use existing bit patterns
to compute a new bit patterns
●
Control: direct the execution of the program

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Adding values stored in memory

Data Transfer

Arithmetic/Logic

Control 10
Fig. 5.2
Dividing values stored in memory

Fig. 5.3
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Parts of a Machine Instruction
●
Op-code: Specifies which operation to execute
● Operand: Gives more detailed information about
the operation
– Interpretation of operand varies depending
on op-code
Computer instruction

Field specifying the Field specifying the

operation to be data To be operated
executed on 13
The composition of an instruction for the
machine

Fig. 5.5
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An encoded version of the instructions in
Figure 5.2

Fig. 5.7
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Program Execution
●
Controlled by two special-purpose
registers
– Program counter: address of next instruction
● – Instruction register: current instruction
Machine Cycle
– Fetch
– Decode
– Execute

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The machine cycle

Fig. 5.8
18
Decoding the instruction B258

Fig. 5.9
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The program is stored in main memory ready for
execution

00

FF

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Fig. 5.10.a
 Performing the fetch step of the machine cycle
● At the beginning of the first fetch:
– Program Counter = A0

Registers Program

Counter
0 A0
2 Instruction
Register

…
6C 02
6D 03 21
Fig. 5.10.b 6E
 Performing the fetch step of the machine
cycle

Fig.
5.11 22
 Performing the fetch step of the machine
cycle (cont’d)

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Fig. 5.12 a
 Registers
Program
Counter
0 A2
5 Instructio
n Register
6
156C
…
6C 02
6D 03
6E

● At the beginning of the first fetch:

– Instruction at A0 (and A1) loaded into Instruction
– register
Program Counter = 24
Fig. 5.12A2
b
 Program
Registers Counter

0A2
5
02 Instruction
6 156C R
egister

… 02
Load register 5 in main memory cell 6C
6C 6D 03
6E

● CPU analyzes the instruction

● Loads Register 5 with the contents of memory cell address
22
6C.
Fig. 5.13
 Registers Program
Counter

0 A2
5 02 Instruction
Register

…
6C 02
6D 03
● At the beginning of the next fetch: 6E

– Program Counter = A2

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Fig. 5.14
 Register Program
Counter

0 A4

5 02 Instructio
n
Register
6 03 166D
…
Load register 6 in main memory cell 6C 02
6D 6D 03
6E
● Instruction at A2 (and A3) loaded into Instruction
● register Program Counter incremented: A4
● CPU analyzes the instruction
● Loads Register 6 with the contents of memory cell address 25
6D.
Fig. 5.15
 Registers Program

Counter
0 A4

2 02 Instruction
Register

3 03

…
6C 02
6D 03
6E
● At the beginning of the next fetch:
– Program Counter = A4 28
Fig. 5.16
 Program
Registers
Counter

0 05 A6
5 02 Instruction
Register
6 03 5056
…
6C
Add: result into register 0, adding 02
Fig. 5.17 contents of register 5 and register 6 6D 03
6E

Adds contents of register 5 and 6, placing result into register

0.
●
Instruction at A4 (and A5) loaded into Instruction
●
register Program Counter incremented: A6
● CPU analyzes the instruction
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● Adds contents of register 5 and register 6, storing the result into register
0.
 Register s Progra
m
Counter
0 05 A6

2 02 Instruction
Register

3 03

…
6C 02
6D 03
6E
● At the beginning of the next fetch:
– Program Counter = A6
30
Fig. 5.18
 Registers Program
Counter

0 05 A8

5 02 Instruction
Register

6 03 306E

6C
…
Store contents of register 0, in 02
memory cell address 6E 6D 03
Fig. 5.19 6E 05

● Instruction at A6 (and A7) loaded into Instruction register

● Program Counter incremented: A8
● CPU analyzes the instruction 31
●
Stores contents of register 0 in the memory cell at address 6E.
 Registers Program

Counter
0 05 A8
2 02 Instructio
n Register

3 03

…
6C 02
6D 03
● At the beginning of the next fetch: 6E 05
– Program Counter = A8

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Fig. 5.20
 Registers Program
Counter

0 05 AA

5 02
Instruction
Register
6 03 C000

…
6C 02
Halt the
program 6D 03
Fig. 5.21 6E 05
● Instruction at A8 (and A9) loaded into Instruction register
● Program Counter incremented: AA
● CPU analyzes the instruction 33
● Halts the program. (Program ends.)
Communicating with Other Devices
●
Controller: An intermediary apparatus that handles
communication between the computer and a
device
– Specialized controllers for each type of device
● – General purpose controllers (USB and Fire Wire)
Port: The point at which a device connects to
● a computer
Memory-mapped I/O: CPU communicates with
peripheral devices as though they were memory cells

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Controllers attached to a machine’s bus

Fig. 5.22
35
A conceptual representation of
memory-mapped I/O

Fig. 5.23
36
 Communicating with Other Devices
(continued)
●
Parallel Communication: Several
communication paths transfer bits simultaneously.
● Serial Communication: Bits are transferred
one after the other over a single communication
path.

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Data Communication Rates
●
Measurement units
– Bps: Bits per second
– Kbps: Kilo-bps (1,000 bps)
– Mbps: Mega-bps (1,000,000 bps)
– Gbps: Giga-bps (1,000,000,000
● bps)
Bandwidth: Maximum available rate

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Thank You!

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