Chapter 5

Register Transfer Languages

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 Chapter Outline

• Micro-operations
• RTL
• RTL specifications
• Realizing RTL specifications
• VHDL

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 Micro-operations

• Specify data transfer

• Do not specify conditions under which
transfers occur
• Do not specify hardware implementation

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Example: X  Y
X

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 Register Transfer Language

• Specify micro-operations and when they

occur
• Format: conditions: micro-operations

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Example: α: X  Y
X

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Simultaneous Data Transfers
α: X  Y, Y  Z

Q D

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Invalid Simultaneous Transfers
α: X  Y, X  Z

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Loading Constant Values into
Registers
α: X  0
β: X  1

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Making Transfers Mutually
Exclusive

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 Multi-bit Data Transfers
α: X  Y

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Bit and Bit-range Transfers

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Arithmetic and Logical Micro-
operations

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Shift Micro-operations

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 Specifying Digital
Components: D Flip-Flop

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Specifying Digital Components:
JK Flip-Flop

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Specifying Digital Components:
Left Shift Register

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Specifying Simple Systems

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System Implementation – Data
Paths

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System Implementation – Data
Paths and Control

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System Implementation Using a
Bus and 3-State Buffers

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System Implementation Using
a Bus and a Multiplexer

n o j

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 Modulo 6 Counter

• Counts up when U = 1
• Count sequence: 000  001  010 
011  100  101  000 …
• V is 3-bit output = count value
• C is 1-bit output = 1 when V = 000

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Modulo 6 Counter State Table

111
111

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Modulo 6 Counter State Diagram

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Modulo 6 Counter RTL
Specification

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Modulo 6 Counter System
Implementation

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Modulo 6 Counter Another
System Implementation

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 Toll Booth Controller

• C = 1 when car is at toll booth

• I[1..0] indicates coin input
• Outputs R, G, A:
– Car in toll booth, toll not fully paid: R = 1
– Toll paid: G = 1
– Car left without paying full toll: R = 1, A = 1

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Toll Booth Controller States

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Toll Booth Controller State Table

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Toll Booth Controller State Diagram

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Toll Booth Controller State
Assignments

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Converting State Transitions
to RTL Code

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Converting State Transitions to
RTL Code

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 Toll Booth Controller RTL
Specification (excluding outputs)

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Toll Booth Controller RTL
Specification (outputs)

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 VHDL – VHSIC Hardware
Description Language
• Formal syntax – portable
• Platform independent
• Design for PLDs, ASICs, or custom
chips
• Simulate designs
• Different levels of abstraction

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 VHDL Design Structure

• Library section
• Entity section
• Architecture section

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VHDL Library Section

library IEEE;
use IEEE.std_logic_1164.all;

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VHDL Entity Section

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VHDL Architecture Section

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 VHDL – High Level of
Abstraction
• Modulo 6 counter
• Designed as a state machine

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Modulo 6 Counter – Library
and Entity Sections

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Modulo 6 Counter – One State

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Architecture Section – State
Generation

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Architecture Section – State
Generation (continued)

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Architecture Section – State
Transition

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VHDL – Low Level of Abstraction

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 VHDL – Advanced
Capabilities
• Components
• Timing
• Simulation

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 Summary

• Micro-operations
• RTL
• RTL specifications
• Realizing RTL specifications
• VHDL

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