Chapter 7

Microsequencer Control Unit

Design

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 Chapter Outline
Basic Microsequencer Design
Very Simple Microsequencer
Relatively Simple Microsequencer
Reducing the Number of
Microinstructions
Microcoded vs. Hardwired Control
Pentium Microprocessor

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 Micro-stuff

Micro-operations
Microinstructions
Microprograms

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Generic Microsequencer

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 Generating the Next Address

Current Address + 1
Address specified by microinstruction
Microsubroutine register
Mapping hardware

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Microinstruction Format

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 Types of Microcode

Horizontal
Vertical
Direct

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A Very Simple Microsequencer

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Mapping Logic

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State Addresses
State Address
FETCH1 0000 (0)
FETCH2 0001 (1)
FETCH3 0010 (2)
ADD1 1000 (8)
ADD2 1001 (9)
AND1 1010 (10)
AND2 1011 (11)
JMP1 1100 (12)
INC1 1110 (14)

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 Partial Microcode
State Address SEL ADDR
FETCH1 0000 (0) 0 0001
FETCH2 0001 (1) 0 0010
FETCH3 0010 (2) 1 XXXX
ADD1 1000 (8) 0 1001
ADD2 1001 (9) 0 0000
AND1 1010 (10) 0 1011
AND2 1011 (11) 0 0000
JMP1 1100 (12) 0 0000
INC1 1110 (14) 0 0000

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Micro-operations
Mnemonic Micro-Operation
ARPC ARPC
ARDR ARDR[5..0]
PCIN PCPC + 1
PCDR PCDR[5..0]
DRM DRM
IRDR IRDR[7..6]
PLUS ACAC + DR
AND ACAC^DR
ACIN ACAC + 1

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Preliminary Horizontal
Microcode

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Optimized Horizontal
Microcode

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Control Signals

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Generic Vertical Microcode
Decoding

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 Field Assignments

Simultaneous micro-operations in
different fields

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 Field Assignments

Simultaneous micro-operations in
different fields
Include a NOP in each field

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 Field Assignments

Simultaneous micro-operations in
different fields
Include a NOP in each field
Distribute remaining micro-operations to
minimize total number of bits required

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 Field Assignments

Simultaneous micro-operations in
different fields
Include a NOP in each field
Distribute remaining micro-operations to
minimize total number of bits required
Group together micro-operations that
modify the same register

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Micro-operation Assignments

M1 M2
NOP NOP
DRM PCIN

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Micro-operation Assignments

M1 M2
NOP NOP
DRM PCIN
ACIN PCDR
PLUS ARPC
AND AIDR

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Micro-operation Assignments

M1 M2
NOP NOP
DRM PCIN
ACIN PCDR
PLUS ARPC
AND
AIDR
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Micro-operation Assignments
and Field Values

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Vertical Microcode

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Micro-operation Generation

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Nanoinstructions

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 Directly Generating Control
Signals
Output control signals instead of micro-
operations
No external decoding required
No external hardware required to
generate control signals
More difficult to code

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Preliminary Direct Microcode

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Optimize Direct Microcode

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 Relatively Simple
Microsequencer
No changes to
Instruction set
Data paths
ALU

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Modified State Diagram

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Microsequencer Hardware

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State Assignments

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Condition Values

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Branch Types

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Branch Logic

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Partial Microcode

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Partial Microcode (continued)

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Micro-operations

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Horizontal Microcode

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Horizontal Microcode

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Horizontal Microcode

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Control Signals

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 Reducing the Number of
Microinstructions
Microsubroutines
Microcode Jumps

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Microsubroutines

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Revised State Assignments

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Microsequencer with
Microsubroutines

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Revised Branch Types

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Revised Branch Logic

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Revised Microcode

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Microcode Jumps

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Revised Microcode

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Microprogrammed Control vs.
Hardwired Control
Complexity of the instruction set

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Microprogrammed Control vs.
Hardwired Control
Complexity of the instruction set
Ease of modification

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Microprogrammed Control vs.
Hardwired Control
Complexity of the instruction set
Ease of modification
Clock speed

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The Pentium Microprocessor

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 Summary
Basic Microsequencer Design
Very Simple Microsequencer
Relatively Simple Microsequencer
Reducing the Number of
Microinstructions
Microcoded vs. Hardwired Control
Pentium Microprocessor

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