Chapter 4 Processor

Chapter 4 Processor
CENTRAL PROCESSING UNIT
• Introduction
• General Register Organization
• Stack Organization
• Instruction Formats
• Addressing Modes
• Data Transfer and Manipulation
cpe 252: Computer Organization 2
• Program Control
4.1 Introduction
• The functional blocks in a computer are of four types:

1. Central Processing Unit
2. Memory
3. Input Unit
4. Output Unit
• The CPU is the brain of the computer.
• It is the part that actually executes

the instructions.
3
• The computer’s CPU fetches, decodes, and
executes program instructions.
• The two principal parts of the CPU are the datapath
and the control unit.
– The datapath consists of an arithmetic-logic unit and
storage units (registers) that are interconnected by a data
bus that is also connected to main memory.
– Various CPU components perform sequenced operations
according to signals provided by its control unit.
4
Major Components
• ALU (arithmetic logic unit): Performs calculations and comparisons (data changed)
• CU (control unit): The control unit determines which actions to carry out according to the
values in a program counter register and a status register.
– performs fetch/execute cycle
– Functions:
• Moves data to and from CPU registers and other hardware components (no change in data)
• Accesses program instructions and issues commands to the ALU
– Subparts:
• Memory management unit: supervises fetching instructions and data
• I/O Interface: sometimes combined with memory management unit as Bust Interface Unit
• Registers
– Registers hold data that can be readily accessed by the CPU.
– They can be implemented using D flip-flops.
– A 32-bit register requires 32 D flip-flops.
– Example: Program counter (PC) or instruction pointer determines next instruction for
execution
5
6
Registers
• Small, permanent storage locations within the CPU used for a
particular purpose
– Scratchpad for currently executing program
• Holds data needed quickly or frequently
– Stores information about status of CPU and currently executing program
• Address of next program instruction
• Signals from external devices
• Manipulated directly by the Control Unit
• Wired for specific function
• Size in bits or bytes (not MB like memory)
• Can hold data, an address or an instruction
7
Types of Registers
• User visible registers
– A user visible register is simply a register than can be referenced
with the machine language of the processor •
– Four categories
• General Purpose
• Data
• Address
• Condition Codes
• Control and Status Registers
8
General Purpose
• General Purpose Registers

– User-visible registers
– Hold intermediate results or data values, e.g., loop counters
– Typically several dozen in current CPUs
• May be true general purpose (all registers are the same)

– Orthogonal to the instruction set: any register can hold any
operand for any instruction (clearly not the case with X86!)
– May be restricted (each register has special functions)
• In some machines GP registers can be used for data or
addressing
9
• In other machines there is a separation:
– Data: Accumulator and count registers
– Addressing: Segment, index, autoindex registers – Stack pointer
• Even on machines with true general purpose registers, if there is
user-visible stack addressing then the stack pointer is special
purpose
• Condition Codes
– Typically partially user-visible •
– Sets of individual bits — e.g. result of last operation was zero
– Can be read (implicitly) by programs — e.g. Jump if zero
– Cannot (usually) be set directly (addressed) by programs — X86 has direct ops for carry
flag only
• STC, CLC, CMC
• BT (Bit Test) Instruction
10
• Special purpose Registers
– Program Count Register (PC)
• Also called instruction pointer
– Instruction Register (IR)
• Stores instruction fetched from memory
– Memory Address Register (MAR)
– Memory Data Register (MDR)
– Status Registers
• Status of CPU and currently executing program
• Flags (one bit Boolean variable) to track condition like
arithmetic carry and overflow, power failure, internal
computer
11
CPU Register Lengths
• The register lengths (number of flip-flops to store bits) are determined by
number of memory locations (address space) and the bus width (in bits)
that determines the number of bits transferred between Memory and
CPU, or between I/O channels and CPU.
PC
12 bits
AR
16 bits
DR
IR
AC
8 bits
INR
4 bits
OUTR
1 bit
SCR
1 bit
R
GENERAL REGISTER
ORGANIZATION
Input
Clock
R1
R2
R3
R4
R5
R6
R7
Load
(7 lines)
SELA { MUX MUX } SELB
3x8
A bus B bus
decoder
SELD
OPR ALU
Output

Operation on Registers
• Stores values from other locations (registers

and memory)
• Addition and subtraction
• Shift or rotate data
• Test contents for conditions such as zero or
positive
14
Operation of Memory
• Each memory location has a unique address

• Address from an instruction is copied to the
MAR which finds the location in memory
• CPU determines if it is a store or retrieval
• Transfer takes place between the MDR and
memory
• MDR is a two way register
15
Relationship between MAR,
MDR and Memory
Data
Address
16
Control Unit
• It is responsible for directing and coordinating
most of the computer system activities.
• It does not execute instructions by itself. It tells
other parts of the computer system what to do.
• It determines the movement of electronic signals
between the main memory and arithmetic logic
unit as well as the control signals between the
CPU and input/output devices.
Control Unit(Condt…)
• To complete an event i.e. processing, control
unit repeats a set of four basic operations:
– Fetching is the process of obtaining a program
instruction or data item from the memory
– Decoding is the process of translating the instruction
into commands the computer can execute.
– Executing is the process of carrying out the
commands.
– Storing is the process of writing the result to
memory.
• The internal communication inside a computer that
transforms raw data into useful information is called
processing.
• To perform this transformation, the computer uses two
components- processor and memory
• The program is fed into the computer through the input unit
and stored in the memory
• To execute the program, the instructions have to be fetched
from memory one by one which is done by control unit
• Then the control unit decodes the instruction.
• According to instruction, control unit issues
signals to other units.
• After instruction is executed, the result of the
instruction is stored in memory or stored
temporarily in the registry, so that this can be
used by the next instruction.
• The results of a program are taken out of the
computer through the output unit.
OPERATION OF CONTROL UNIT
The control unit directs the information flow through ALU by:
- Selecting various Components in the system
- Selecting the Function of ALU

Example: R1 <- R2 + R3
[1] MUX A selector (SELA): BUS A  R2
[2] MUX B selector (SELB): BUS B  R3
[3] ALU operation selector (OPR): ALU to ADD

3 3 3 5
[4] Decoder destination selector (SELD): R1  Out Bus
Control Word SELA SELB SELD OPR
Encoding of register selection fields

Binary
Code SELA SELB SELD
000 Input Input None
001 R1 R1 R1
010 R2 R2 R2
011 R3 R3 R3
100 R4 R4 R4
101 R5 R5 R5
110 R6 R6 R6
111 R7 R7 R7
Arithmetic Logic unit
• The ALU contains electronic circuits necessary
to perform arithmetic and logical operations.
• The arithmetic operations are ADD,
SUBSTRACT, MULTIPLY, DIVIDE, etc.
• The logical operations include COMPARE,
SHIFT, ROTATE, AND, OR, etc
• The control unit analyses each instruction in the
program and sends the relevant signals to all
other units – ALU, Memory, Input unit and
Output unit
Control
ALU CONTROL
Encoding of ALU operations OPR

Select Operation Symbol
00000 Transfer A TSFA
00001 Increment A INCA
00010 ADD A + B ADD
00101 Subtract A - B SUB
00110 Decrement A DECA
01000 AND A and B AND
01010 OR A and B OR
01100 XOR A and B XOR
01110 Complement A COMA
10000 Shift right A SHRA
11000 Shift left A SHLA
Symbolic Designation
Examples of ALU Microoperations Microoperation SELA SELB SELD OPR Control Word
R1  R2 - R3 R2 R3 R1 SUB 010 011 001 00101
R4  R4  R5 R4 R5 R4 OR 100 101 100 01010
R6  R6 + 1 R6 - R6 INCA 110 000 110 00001
R7  R1 R1 - R7 TSFA 001 000 111 00000
Output  R2 R2 - None TSFA 010 000 000 00000

cpe 252: Computer Organization
Output  Input Input - None TSFA 000 000 000 00000
R4  shl R4 R4 - R4 SHLA 100 000 100 11000

A Simple Program
• Want to add values of variables a and b

(assumed to be in memory), and put the
result in variable c in memory, I.e. c  a+b
• Instructions in program
– Load a into register r1
– Load b into register r3
– r2  r1 + r3
– Store r2 in c
Running the Program
2 a
1 c
3 b
r1 2
r2
r3
Logic Memory
r4
Load a into r1 2005

IR Load a into r1
Load b into r3 2006
IP 2005
r2 r1 + r3 2007
Store r2 into c 2008

CPU
Running the Program
2 a
1 c
3 b
r1 2
r2
r3 3
Logic Memory
r4
Load a into r1 2005

IR Load b into r3
Load b into r3 2006
IP 2006
r2 r1 + r3 2007

CPU
Running the Program
2 a
1 c
3 b
r1 2
r2 5
r3 3
Logic Memory
r4
Load a into r1 2005

IR r2  r1 + r3
Load b into r3 2006
IP 2007
r2 r1 + r3 2007

CPU
Running the Program
2 a
1 c
3 b
r1 2
r2 5
r3 3
Logic Memory
r4
Load a into r1 2005

IR Store r2 into c
Load b into r3 2006
IP 2008
r2 r1 + r3 2007

CPU
Running the Program
2 a
5 c
3 b
r1 2
r2 5
r3 3
Logic Memory
r4
Load a into r1 2005

IR Store r2 into c
Load b into r3 2006
IP 2008
r2 r1 + r3 2007

CPU
Where we are
• Examined the hardware for a computer
– Truth tables
– Logic gates
– States and transitions in a state machine
– The workings of a CPU and Memory
• Now, want to program the hardware

Programs and Instructions
• Programs are made up of instructions
• CPU executes one instruction every clock cycle
• Modern CPUS do more, but we ignore that
• Specifying a program and its instructions:
• Lowest level: Machine language
• Intermediate level: Assembly language
• Typically today: High-level programming language

Specifying a Program and its Instructions
• High-level programs: each statement translates to many instructions

Load a into r1
• E.g. c  a + b to: Load b into r3
r2  r1 + r3
Store r2 into c
• Assembly language: specify each machine instruction, using mnemonic form
• E.g. Load r1, A
• Machine language: specify each machine instruction, using bit patterns
• E.g. 1101101000001110011
Machine/Assembly Language
• We have a machine that can execute instructions
• Basic Questions:
• What instructions?
• How are these instructions represented to the computer hardware?

Stored Programs
• A stored program is a set of instructions and data
expressed in binary language, stored in non-volatile (ie.
disk storage) memory
• Programs can be executed only from Memory.

– Thus, a program must be loaded from disk to RAM in
order to execute it.
– Loaded programs are called processes.
– Individual instructions must be transferred to the CPU
where they are executed, using data that must be obtained
from either CPU registers or RAM
• A process is executed by executing each individual

instruction that, collectively, fulfill the intentions of the
programmer.
Instructions
• Instruction
– Direction given to a computer
– Causes electrical signals to be sent through specific circuits for
processing
Chapter 7 CPU and Memory 7-35

Instruction Architecture
• The list of all instructions engineered for a computer’s CPU

is called the instruction set.
• To distinguish each instruction, they are assigned a unique
numeric code
– Can be done in many ways
– Does not need to be ordinal (ie. starting from 0 and
running contiguously)
– Can be partially ordinal and partially hierarchical
• Mano’s approach
• Instructions must be capable of referencing Memory and/or
CPU addresses in order to cause data to be transferred and
operated on.
Instruction Architecture
• Instructions consist of
– Operation code data
– Address data
– Mode data
• Direct addressing – data found at the specified address
• Indirect addressing – data found at the address found at the
specified address
The number of memory (pointer
referenced operands variesconcept)
from computer to computer.
0 Mano simplifies the instruction architecture to permit zero or one memory address field. In the case of Indirect
addressing mode there are two memory accesses, but only one reference.
1
15 14 12 11 0
IR
Mode bit I OpCode Address
Instructions set Design
• Instruction set
– Design defines functions performed by the processor
– Differentiates computer architecture by the
• Number of instructions
• Complexity of operations performed by individual instructions
• Data types supported
• Format (layout, fixed vs. variable length)
• Use of registers
• Addressing (size, modes)
Chapter 7 CPU and Memory 7-38

Instruction Hierarchy
• It is desirable to engineer the computer to support a
reasonable number of independent instructions
– Examples:
• Add, subtract, transfer, shift, logic, comparison, branch,
input, output
– 4 bits can be used to support 24 = 16 unique
instructions
• Leaves 12 bits to represent an address space of 4096 words
– However, 16 instructions is not enough for most
program needs
15 14 12 11 0
IR
I OpCode Address
• It is desirable to engineer the computer to support a
reasonable number of independent instructions
– Use a hierarchical scheme (1+3 scheme)
• OpCode – 3 bits – supports 8 unique codes
– 0-6 (instructions)
– 7 (toggle)
• Mode – 1 bit – supports 2 addressing modes
– I=0 Direct addressing
– I=1 Indirect addressing
• Special Case :: OpCode = 7 (toggle) PLUS Mode bit (I)
– Use 12 bits of Address field to specify additional instructions
15 14 12 11 0
IR
I OpCode Address
• Mano’s instruction set consists of 25 instructions:
Instruction
OpCode (0-6) OpCode (7)
Direct (I=0) Indirect (I=1) Direct (I=0) Indirect (I=1)
4 bit code 4 bit code 16 bit code 16 bit code
0 AND 8 AND 7800 CLA F800 INP
1 ADD 9 ADD 7400 CLE F400 OUT
2 LDA A LDA 7200 CMA F200 SKI
3 STA B STA 7100 CME F100 SKO
4 BUN C BUN 7080 CIR F080 ION
5 BSA D BSA 7040 CIL F040 IOF
6 ISZ E ISZ 7020 INC 6

12
7
7010 SPA
7008 SNA
Instruction Set Completeness
• Selection of instructions should span a variety of applications
suitable to support programming
An important issue for many applications is the number of programmable (general purpose)
registers.
– Arithmetic,
Mano adoptslogical and providing
a minimalist approach shift ainstructions
single such register, the accumulator AC.
This simple case does allow full illustration of all computational requirements of a more
powerful computer with a larger instruction set (but with much added cost to programming).
– Instructions for moving data to and from memory and CPU
Among commercial computers one finds both complex (large number) instruction sets (CISC)
registers
and reduced (number) instruction sets (RISC).
– Program control instructions, instructions that check status

conditions
– Input and Output instructions

Instruction Processing & Instruction Cycle
• Instruction processing cannot occur in a single clock cycle – it is

too complicated !
– Must fetch the instruction from memory and load the instruction
register, IR.
– Must decode the Operation Code to determine whether data must be
fetched and whether we fetch data directly, or indirectly
– Must fetch required data, if any, from memory into CPU
• OR, must store data from CPU into memory
• OR, must obtain data from Input
• OR, must place data for Output
– Must process the data according to instruction logic
• Thus, the instruction cycle consists of a controlled sequence of
microoperations
Timing and Control
• In order to control the steps of the instruction cycle, it is necessary to
introduce a counter, whose output is used as input to the control logic
– We will utilize a Sequence Counter Register (SC, or SCR). This is a register

that holds a count value, can be reset to zero and can be incremented (or
decremented) by one
CLR
SC INC
– Each instruction will require a specified number of time steps to complete a
sequence of microoperations.…… Each step of the sequence is marked by a count
value in SC.
Timing and Control
• The SC outputs a string of bits whose value is in the range from
0 to 2L-1
– Eg. for L=3, from 0 to 7
• We need a way of converting the bit string value to single bit
valued outputs labelled T0, T1, T2, T3, and so on, up to Tx
(where x = 2L-1)
• A decoder serves our purpose, recalling that the output from the
DEC is a 1 only on one line (the rest are 0`s)
Tx T2 T1 T0
CLR
…..
SC INC
L-to-2L DEC
……
…
Timing and Control
• Step 1: Where do we fetch the next instruction from
at T0 (start time)?
– The Program Counter register (PC) is assumed to hold the

address of the next instruction to be executed.
• It is loaded initially during the machine bootstrapping process.
– The PC is transferred to the Address Register (AR) which is

connected to the Address Bus Multiplexer.
• The AR provides the selection input to the address bus multiplexer to
enable RAM-CPU data transfers
PC
T0 : AR = PC Load
AR
Timing and Control
• Step 2: How do we obtain the instruction from

Note how the PC is updated in parallel.
This assumes that the next Memory

instruction (yet to be executed) in logical sequence is actually
memory at T1? located at the next memoryData bus

location.
INC
– The data
This restriction to
stored non-sequential instructionsDR
at the selected
M[AR] is removed by including instructions that
address isPCtransferred
LD
onto the
modify the PC explicitly.
Data Bus and then to the Data Register (DR) in the CPU.
– The instruction data is transferred IR
immediately to the
LD
Instruction Register (IR) CPU bus

AR LD
Address bus
T1 : DR = M[AR] , IR = DR , PC = PC + 1
NOTE: Mano does not include this step explicitly.

However, in most systems the initial transfer from memory is always to a CPU buffer, such as DR. In effect, this is simply a
pipeline element of a transfer circuit that adds an intermediate parallel load through DR to IR.
This can be modified to act as a Master-Slave element which is necessary to build a Direct Memory Access (DMA) control
Timing and Control
• Step 3: How do we decode the instruction intention (ie.

meaning, operational definition) at T2?
–NOTE:
The OpCode, Mode and Address field bits all serve as inputs
All instructions share the steps T0, T1 and T2.
to the Control Logic Gates that select the specific instruction
However, depending on what each specific instruction
semantics
requires, the control logic for higher time steps is more
• Direct addressing
complicated, requiring more inputs.
• Indirect addressing Note the reference to a DECoder unit to

explicitly access the IR bits indicated
• CPU register addressing
• Input
• Output
T2 : {D0,...,D7} = DEC( IR(12-14) ),
AR = IR(0-11),
I = IR(15) The AR may be directly connected to

the IR address bits indicated
Timing and Control
• The instruction cycle consists of a controlled sequence of
microoperations using control logic gates and a sequence counter.
I OpCode Address
IR 15 14 13 12 11 0
Connect it all together !

2 1 0
3x8 DEC Enable one specific

7 6 5 4 3 2 1 0
logic circuit
Signal the SC to advance
Control (INC) to next timing value,

Logic
or reset.
Control
Gates
Outputs
F E D C B A 9 ... 1 0
Timing inputs
4x16 DEC
3 2 1 0
Clock has not
4-bit been included!

INC
Sequence CLR
Counter (SC)
Instruction Format
INSTRUCTION FORMAT
Instruction Fields
OP-code field - specifies the operation to be performed
Address field - designates memory address(s) or a processor register(s)
Mode field - specifies the way the operand or the
effective address is determined

The number of address fields in the instruction format
depends on the internal organization of CPU
- The three most common CPU organizations:

Single accumulator organization:
ADD X /* AC  AC + M[X] */
General register organization:
ADD R1, R2, R3 /* R1  R2 + R3 */
ADD R1, R2 /* R1  R1 + R2 */
MOV R1, R2 /* R1  R2 */
ADD R1, X /* R1  R1 + M[X] */
Stack organization:
PUSH X
cpe 252: Computer Organization
/* TOS  M[X] */
50
ADD
THREE, and TWO-ADDRESS INSTRUCTIONS
Three-Address Instructions:
Program to evaluate X = (A + B) * (C + D) :
ADD R1, A, B /* R1  M[A] + M[B] */
ADD R2, C, D /* R2  M[C] + M[D] */
MUL X, R1, R2 /* M[X]  R1 * R2 */
- Results in short programs

- Instruction becomes long (many bits)
Two-Address Instructions:
Program to evaluate X = (A + B) * (C + D) :
MOV R1, A /* R1  M[A] */

ADD R1, B /* R1  R1 + M[B] */
MOV cpe
R2,252:
C /* R2 Organization
Computer M[C] */ 51
ADD R2, D /* R2  R2 + M[D] */
ONE, and ZERO-ADDRESS INSTRUCTIONS
One-Address Instructions:
- Use an implied AC register for all data manipulation
- Program to evaluate X = (A + B) * (C + D) :
LOAD A /* AC  M[A] */
ADD B /* AC  AC + M[B] */
STORE T /* M[T]  AC */
LOAD C /* AC  M[C] */
ONE, and ZERO-ADDRESS INSTRUCTIONS
ADD D /* AC  AC + M[D] */
MUL T /* AC  AC * M[T] */
- Can be found
STORE X in a stack-organized
/* M[X]  AC computer
*/
Zero-Address Instructions:
- Program to evaluate X = (A + B) * (C + D) :
PUSHA /* TOS  A */
PUSHB /* TOS  B */
ADD /* TOS  (A + B) */
PUSHC /* TOS  C */
PUSHD /* TOS  D */
ADD /* TOS  (C + D) */
MUL /* TOS  cpe
(C + 252:
D) * (AComputer
+ B) */ Organization 52
POP X /* M[X]  TOS */
ADDRESSING MODES
Addressing Modes:
* Specifies a rule for interpreting or modifying the
address field of the instruction (before the operand
is actually referenced)
* Variety of addressing modes
- to give programming flexibility to the user
- to use the bits in the address field of the
instruction efficiently

TYPES OF ADDRESSING MODES
Implied Mode
Address of the operands are specified implicitly
in the definition of the instruction
- No need to specify address in the instruction
- EA = AC, or EA = Stack[SP], EA: Effective Address .
Immediate Mode
Instead of specifying the address of the operand,
operand itself is specified
- No need to specify address in the instruction
- However, operand itself needs to be specified
- Sometimes, require more bits than the address
- Fast to acquire an operand
Register Mode
cpe 252:
Address specified in the instruction Computer
is the Organization
register address 54
- Designated operand need to be in a register
Register Indirect Mode

Instruction specifies a register which contains
the memory address of the operand
- Saving instruction bits since register address
is shorter than the memory address
- Slower to acquire an operand than both the
register addressing or memory addressing
- EA = [IR(R)] ([x]: Content of x)
Auto-increment or Auto-decrement features:

Same as the Register Indirect, but:
- When the address in the register is used to access memory, the value in the register is incremented
or decremented by 1 (after or before the execution of the instruction)

Direct Address Mode
Instruction specifies the memory address which
can be used directly to the physical memory
- Faster than the other memory addressing modes
- Too many bits are needed to specify the address
for a large physical memory space
- EA = IR(address), (IR(address): address field of IR)
Indirect Addressing Mode

The address field of an instruction specifies the address of a memory location that contains the address of the operand
- When the abbreviated address is used, large physical memory can be addressed with a relatively small number of
bits
- Slow to acquire an operand because of an additional memory access
- EA = M[IR(address)]

Relative Addressing Modes
The Address fields of an instruction specifies the part of the address (abbreviated address) which can be used along
with a designated register to calculate the address of the operand
PC Relative Addressing Mode(R = PC)
- EA = PC + IR(address)
- Address field of the instruction is short

- Large physical memory can be accessed with a small number of address bits
Indexed Addressing Mode

XR: Index Register:
- EA = XR + IR(address)
Base Register Addressing Mode
BAR: Base Address Register:
- EA = BAR + IR(address)
ADDRESSING MODES - EXAMPLES
Address Memory
200 Load to AC Mode
201 Address = 500

PC = 200
202 Next instruction
R1 = 400
399 450
XR = 100
400 700
AC
500 800
Addressing Effective Content

Mode Address of AC
Direct address 500 /* AC  (500) */ 800 600 900
Immediate operand - /* AC  500 */ 500

Indirect address 800 /* AC  ((500)) */ 300
Relative address 702 /* AC  (PC+500) */ 325 702 325
Indexed address 600 /* AC  (XR+500) */ 900

Register - /* AC  R1 */ 400
Register indirect 400 /* AC  (R1) */ 700 800 300
Autoincrement 400 /* AC  (R1)+ */ 700
Autodecrement 399 /* AC  -(R) */ 450

DATA TRANSFER INSTRUCTIONS
Typical Data Transfer Instructions
Name Mnemonic
Load LD
Store ST
Move MOV
Exchange XCH
Input IN
Output OUT
Push PUSH
Pop POP
Data Transfer Instructions with Different Addressing Modes
Assembly
Mode Register Transfer
Convention
Direct address LD ADR AC M[ADR]
Indirect address LD @ADR AC  M[M[ADR]]
Relative address LD $ADR AC  M[PC + ADR]
Immediate operand LD #NBR AC  NBR
Index addressing LD ADR(X) AC  M[ADR + XR]
Register LD R1 AC  R1
Register indirect LD (R1) AC  M[R1]
Autoincrement LD (R1)+ AC  M[R1], R1  R1 + 1
Autodecrement LD -(R1) R1  R1 - 1, AC  M[R1]

DATA MANIPULATION INSTRUCTIONS
Three Basic Types: Arithmetic instructions
Logical and bit manipulation instructions
Shift instructions
Arithmetic Instructions
Name Mnemonic
Increment INC
Decrement DEC
Add ADD
Subtract SUB
Multiply MUL
Divide DIV
Add with Carry ADDC
Subtract with Borrow SUBB
Negate(2’s Complement) NEG
Logical and Bit Manipulation Instructions Shift Instructions
Name Mnemonic Name Mnemonic
Clear CLR Logical shift right SHR
Complement COM Logical shift left SHL
AND AND Arithmetic shift right SHRA
OR OR Arithmetic shift left SHLA
Exclusive-OR XOR Rotate right ROR
Clear carry CLRC Rotate left ROL
Set carry SETC Rotate right thru carry RORC
Complement carry COMC Rotate left thru carry ROLC
Enable interrupt EI
Disable interrupt DI
PROGRAM CONTROL INSTRUCTIONS
+1
In-Line Sequencing
(Next instruction is fetched from the
PC next adjacent location in the memory)
Address from other source; Current Instruction, Stack, etc

Branch, Conditional Branch, Subroutine, etc
Program Control Instructions
Name Mnemonic
Branch BR
Jump JMP
Skip SKP
Call CALL
* CMP and TST instructions do not retain their
Return RTN
results of operations(- and AND, respectively).
Compare(by - ) CMP
They only set or clear certain Flags.
Test (by AND) TST
Status Flag Circuit A B

8 8
c
7
8-bit ALU
c
8 F -F
7 0
V Z S C
F
7
Check for 8
zero output
F 252: Computer Organization

cpe 61
CONDITIONAL BRANCH INSTRUCTIONS
Mnemonic Branch condition Tested condition
BZ Branch if zero Z=1

BNZ Branch if not zero Z=0
BC Branch if carry C=1
BNC Branch if no carry C=0
BP Branch if plus S=0
BM Branch if minus S=1
BV Branch if overflow V=1
BNV Branch if no overflow V=0
Unsigned compare conditions (A - B)

BHI Branch if higher A>B
BHE Branch if higher or equal AB
BLO Branch if lower A<B
BLOE Branch if lower or equal AB
BE Branch if equal A=B
BNE Branch if not equal AB
Signed compare conditions (A - B)
BGT Branch if greater than A>B

BGE Branch if greater or equal AB
BLT Branch if less than A<B
BLE Branch if less or equal AB
BE Branch if equal A=B
BNE Branch if not equal AB

SUBROUTINE CALL AND RETURN
Call subroutine
SUBROUTINE CALL
Jump to subroutine
Branch to subroutine
Branch and save return address
Two Most Important Operations are Implied;
* Branch to the beginning of the Subroutine
- Same as the Branch or Conditional Branch
* Save the Return Address to get the address

of the location in the Calling Program upon
exit from the Subroutine
- Locations for storing Return Address: CALL
SP  SP - 1
• Fixed Location in the subroutine(Memory) M[SP]  PC
• Fixed Location in memory PC  EA
• In a processor Register
• In a memory stack RTN
- most efficient way PC  M[SP]

SP  SP + 1

Types of Interrupts:
PROGRAM INTERRUPT
External interrupts
External Interrupts initiated from the outside of CPU and Memory
- I/O Device -> Data transfer request or Data transfer complete
- Timing Device -> Timeout
- Power Failure
Internal interrupts (traps)

Internal Interrupts are caused by the currently running program
- Register, Stack Overflow
- Divide by zero
- OP-code Violation
- Protection Violation
Software Interrupts
Both External and Internal Interrupts are initiated by the computer Hardware.
Software Interrupts are initiated by texecuting an instruction.
- Supervisor Call -> Switching from a user mode to the supervisor mode
-> Allows to execute a certain class of operations
which are not allowed in the user mode

INTERRUPT PROCEDURE
Interrupt Procedure and Subroutine Call
- The interrupt is usually initiated by an internal or
an external signal rather than from the execution of
an instruction (except for the software interrupt)
- The address of the interrupt service program is
determined by the hardware rather than from the
address field of an instruction
- An interrupt procedure usually stores all the
information necessary to define the state of CPU
rather than storing only the PC.
The state of the CPU is determined from;
Content of the PC
Content of all processor registers
Content of status bits
Many ways of saving the CPU state depending on the CPU architectures

RISC: REDUCED INSTRUCTION SET
COMPUTERS
Historical Background
IBM System/360, 1964
- The real beginning of modern computer architecture

- Distinction between Architecture and Implementation
- Architecture: The abstract structure of a computer
seen by an assembly-language programmer
Compiler -program
High-Level Instruction
Hardware
Language Set
Architecture Implementation
Continuing growth in semiconductor memory and microprogramming

-> A much richer and complicated instruction sets
=> CISC(Complex Instruction Set Computer)
- Arguments advanced at that time

Richer instruction sets would simplify compilers
Richer instruction sets would alleviate the software crisis
- move as much functions to the hardware as possible
- close Semantic Gap between machine language
and the high-level language
Richer instruction sets would improve the architecture quality

COMPLEX INSTRUCTION SET COMPUTERS: CISC
High Performance General Purpose Instructions
Characteristics of CISC:
1. A large number of instructions (from 100-250 usually)
2. Some instructions that performs a certain tasks are not used frequently.
3. Many addressing modes are used (5 to 20)
4. Variable length instruction format.
5. Instructions that manipulate operands in memory.

PHYLOSOPHY OF RISC
Reduce the semantic gap between
machine instruction and microinstruction
1-Cycle instruction
Most of the instructions complete their execution

in 1 CPU clock cycle - like a microoperation
* Functions of the instruction (contrast to CISC)

- Very simple functions
- Very simple instruction format
- Similar to microinstructions
=> No need for microprogrammed control
* Register-Register Instructions
- Avoid memory reference instructions except
Load and Store instructions
- Most of the operands can be found in the
registers instead of main memory
=> Shorter instructions
=> Uniform instruction cycle
=> Requirement of large number of registers
* Employ instruction pipeline

CHARACTERISTICS OF RISC
Common RISC Characteristics
- Operations are register-to-register, with only LOAD and STORE accessing memory
- The operations and addressing modes are reduced
Instruction formats are simple

CHARACTERISTICS OF RISC
RISC Characteristics
- Relatively few instructions
- Relatively few addressing modes
- Memory access limited to load and store instructions
- All operations done within the registers of the CPU
- Fixed-length, easily decoded instruction format
- Single-cycle instruction format
- Hardwired rather than microprogrammed control
More RISC Characteristics
-A relatively large numbers of registers in the processor unit.

-Efficient instruction pipeline
-Compiler support: provides efficient translation of high-level language
programs into machine language programs.
Advantages of RISC
- VLSI Realization
- Computing Speed
- Design Costs and Reliability
- High Level Language Support

End of Chapter 3A
71

Chapter 4 Processor - 2014

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Chapter 4 Processor - 2014

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CENTRAL PROCESSING UNIT

• The functional blocks in a computer are of four types:

• The CPU is the brain of the computer.

• It is the part that actually executes

• General Purpose Registers

• May be true general purpose (all registers are the same)

cpe 252: Computer Organization 13

• Stores values from other locations (registers

• Each memory location has a unique address

- Selecting various Components in the system

- Selecting the Function of ALU

[2] MUX B selector (SELB): BUS B  R3

[3] ALU operation selector (OPR): ALU to ADD

Encoding of register selection fields

Encoding of ALU operations OPR

R1  R2 - R3 R2 R3 R1 SUB 010 011 001 00101

R4  R4  R5 R4 R5 R4 OR 100 101 100 01010

R6  R6 + 1 R6 - R6 INCA 110 000 110 00001

R7  R1 R1 - R7 TSFA 001 000 111 00000

Output  R2 R2 - None TSFA 010 000 000 00000

R4  shl R4 R4 - R4 SHLA 100 000 100 11000

• Want to add values of variables a and b

Load a into r1 2005

Store r2 into c 2008

Load a into r1 2005

Store r2 into c 2008

Load a into r1 2005

Store r2 into c 2008

Load a into r1 2005

Store r2 into c 2008

Load a into r1 2005

Store r2 into c 2008

• Now, want to program the hardware

• Programs are made up of instructions

• CPU executes one instruction every clock cycle

• Modern CPUS do more, but we ignore that

• Specifying a program and its instructions:

• Lowest level: Machine language

• Intermediate level: Assembly language

• Typically today: High-level programming language

• High-level programs: each statement translates to many instructions

• E.g. c  a + b to: Load b into r3

• Assembly language: specify each machine instruction, using mnemonic form

• E.g. Load r1, A

• Machine language: specify each machine instruction, using bit patterns

• We have a machine that can execute instructions

• How are these instructions represented to the computer hardware?

• Programs can be executed only from Memory.

• A process is executed by executing each individual

Chapter 7 CPU and Memory 7-35

• The list of all instructions engineered for a computer’s CPU

Chapter 7 CPU and Memory 7-38

OpCode (0-6) OpCode (7)

Direct (I=0) Indirect (I=1) Direct (I=0) Indirect (I=1)

4 bit code 4 bit code 16 bit code 16 bit code

0 AND 8 AND 7800 CLA F800 INP

1 ADD 9 ADD 7400 CLE F400 OUT

2 LDA A LDA 7200 CMA F200 SKI

3 STA B STA 7100 CME F100 SKO

4 BUN C BUN 7080 CIR F080 ION

5 BSA D BSA 7040 CIL F040 IOF

6 ISZ E ISZ 7020 INC 6