IMPLEMENTATION OF 16-BIT RISC

PROCESSOR CONTROL UNIT USING VERILOG

•Team:
Paili Bhargavi(319106512074)
Sabeela(319106512075)
Sobha Priyanka(319106512076)
Golla Usha Mounika(319106512077)
•Under Guidance Of:
Dr. G. Rajeswara Rao ,M.Tech,PhD
Adjunct Professor
•Department: Electronics & Communication Engineering
•Andhra University College of Engineering
 OBJECTIVE

• The main objective is designing and implementing a functional 16-bit RISC

processor control unit that is capable of executing a set of predefined
instructions.
• And Improving the performance and efficiency of the control unit by
optimizing the design and reducing the number of clock cycles required for
each instruction.
 ABSTRACT

• The implementation of a 16-bit RISC processor control unit using Verilog is a digital design
project aimed at developing a functional and efficient control unit capable of executing a set of
predefined instructions.
• The project involves designing and simulating the control unit using a hardware description
language, such as Verilog, and verifying its functionality through simulation and testing using
the Xilinx Vivado software tool. The final output of the project is a functional and efficient 16-
bit RISC processor control unit capable of executing a predefined set of instructions.
• The hardwired nature of the processor can be optimized for power and performance, by
reducing the number of clock cycles required for each instruction and minimizing power
consumption. This can make the processor more energy-efficient and suitable for battery-
powered devices.
What is 16-bit RISC processor?
A 16-bit RISC processor is a type of processor that operates on 16-
bit data at a time. It typically has a relatively small set of
instructions, each of which can be executed in a single clock cycle.
This allows it to perform operations quickly, making it suitable for
use in applications that require fast execution times, such as
embedded systems, digital signal processing, and other applications
that require real-time performance.
Brief history of RISC processor
The term "RISC" (Reduced Instruction Set Computer) was coined by David
Patterson, one of the researchers at UC Berkeley, to describe this new
approach to processor design.

The key idea behind RISC processors was to simplify the processor
architecture by reducing the number of instructions and making each
instruction execute in a single clock cycle. This was in contrast to the
prevailing approach at the time, which was to design processors with a large
number of complex instructions that executed in multiple clock cycles.
Why use a RISC processor?
There are several reasons why a RISC (Reduced Instruction Set Computer)
processor might be preferred over other types of processors:

• Faster Execution

• Energy Efficiency.

• High Performance.

• Lower cost

• Ease of Programming.
RISC Processor Architecture
TYPES OF CONTROL UNIT
The control unit is classified into two major categories

• Hardwired control

• Microprogrammed control
 COMPARISION
Microprogrammed control
Hardwired Control
• It is the microprogram in control store • It is the sequential circuit that generates
that generates control signals. control signals.

• Speed of operation is low , because it • Speed of operation is high

involves Memory access.

• Chip area is high • Chip area is low

• Power consumption is high • Power consumption is low

IMPLIMENTATION DIAGRAM
(Control Unit of RISC processor)
Instruction Register
Decoder
A decoder typically consists of a set of inputs that receive coded
signals, a set of output lines that represent decoded signals, and a
combinational logic circuit that decodes the input signals and
generates output signals based on the input signal combination.
Decoders can have various input/output configurations, such as 2-to-4,
3-to-8, 4-to-16, and so on, depending on the number of inputs and
outputs required.

Decoders are widely used in computer memory systems, such as RAM

and ROM, to enable the CPU to access specific memory locations and
retrieve data or instructions.
4 bit sequence counter
A 4-bit sequence counter is a digital circuit that counts in sequence from 0 to
15 in binary. It consists of four flip-flops that are connected in a way that
enables them to count in sequence through the 16 possible states of a 4-bit
binary number.

The counter has four output lines, each representing one bit of the binary
count, and an input line that enables the counter to be reset to 0. The counter
operates on a clock signal that increments the count on each clock pulse.
 SOFTWARE TOOLS

•
•
Features of Verilog
Verilog is a hardware description language (HDL) used to model, design and simulate
digital circuits. Some of the key features of Verilog are:

• Structural modelling

• Behavioural modelling

• Data types

• Hierarchy

• Testbenches

• Synthesis

• Verification
Xilinx Vivado
• Xilinx Vivado is a software suite developed by Xilinx, Inc. for designing and
programming field-programmable gate arrays (FPGAs) and system-on-chip (SoC)
devices. Vivado provides an integrated development environment (IDE) that
supports all stages of the design process, from system-level design and modeling
to implementation and debugging.

• Vivado includes a wide range of tools and features for FPGA design, including
high-level synthesis, simulation, and verification tools, as well as implementation
tools for mapping designs to FPGA resources and generating bitstreams for
device programming
SIMULATION
DIAGRAM OF
HARDWIRED
CONTROL UNIT
Control Signal Pins
Op_and : Control the execution of AND instruction
Op_add : Controls the execution of the ADD instruction.
Op_or : Controls the execution of the OR instruction
Op_sub : Controls the execution of the subtraction instruction
Jump : Controls the execution of the jump instruction
Op_com : Controls the execution of the comparison instruction
Op_shr : Controls the execution of the shift right instruction
Op_shl : Controls the execution of the shift left instruction
Ld[4:0] : Controls the loading of the AR, PC, DR, AC, and IR registers
Inr[3:0] : Controls the incrementing of the AR, PC, DR, and AC registers
Clr [3:0] : Controls the clearing of the AR, PC, DR, and AC registers
Read : Enables reading from memory
Write : Enables writing to memory.
x[7:0] : Encodes the state of the machine for display purposes
 Sub Blocks of Control Unit
3X8 Decoder 4X16 Decoder
Sequence counter
 RTL
SYNTHESIS
RTL synthesis is a process of converting a high-level hardware description language (HDL) like
Verilog into a gate-level netlist that can be used for implementation on an FPGA

The basic steps involved in RTL synthesis of a 16-bit RISC processor control unit using Verilog
are:
• Behavioral description.
• RTL coding.
• Synthesis tool selection.
• Synthesis constraints.
• Synthesis run.
• Netlist verification.
• Optimization.
• Post-synthesis simulation.
• Physical implementation.
 CONTROL
UNIT
WAVEFORMS
The control unit in a 16-bit RISC processor generates control signals that direct the operation of
various components such as the ALU, registers, memory, and I/O devices. The waveforms of the
control unit in a 16-bit RISC processor implementation using Verilog would typically include the
following:
• Clock signal
• Instruction signals.
• Data signals.
• Address signals
• Control signals.

The waveforms of the control unit in a 16-bit RISC processor implementation using Verilog would
typically show the timing and logic of these control signals over time. The waveforms would show the
transitions between high and low states of the control signals and the timing relationships between the
signals. These waveforms are critical for understanding the operation of the processor and for
debugging and optimization purposes.
 Power Estimation

The Power consumption of Hardwired control is less because it is

designed using logic gates and combinational circuits. The minimum
power estimation of hardwired control unit is 0.082w is shown in fig8.
Also, the minimum clock period is 1.591ns which translates a maximum
operating frequency of 628.615MHz. This is done by using Artix7 FPGA.
 ADVANTAGES

• Complex and efficient machine instructions.

• Low power consumption
• Less execution time
• High performance
• It helps to reduce the instruction set.
• It offers extensive addressing capabilities for memory management.
 APPLICATIONS

 Embedded Systems

 Mobile Devices

 Networking

 Gaming

 Digital Signal Processing

 CONCLUSION

• The design architecture of a Hardwired control unit of the 16 bit RISC processor is
designed in Verilog code using Xilinx ISE 14.7 tool for synthesis and simulation. The
extensive simulation has been used to verify the results. The Hardwired control unit
generates control signals without micro code and it faster than other control units. The
control unit achieves higher performance, lower power consumption and lower delay.
The hardwired control unit is used in industrial automation systems and Embedded
Systems to improve processing speed and efficiency.
 REFERENCE

• Ravi Hosamani , Rakesh H. M. , Rakesh B Shettar, Praveen Kumar Y G ,“Realization of

8-Bit Pipelined RISC Processor using Verilog HDL”, 09 Sep 2021, International
Research Journal of Engineering and Technology (IRJET), Karnataka, India.

• Shruthi, Dr. Jamuna S, “Design and Implementation of RISC-V Subsystems using

Verilog HDL”, 06 June 2021, International Research Journal of Engineering and
Technology (IRJET), Bangalore, Karnataka.