VLSI INDUSTRY, DEVICE

TECHNOLOGIES
{CMOS, SOI, FINFET &
GAAFET} AND STREAMS

Lakshmi Narasaiah .M
 HOW BIG IS IT?
• VLSI Semiconductors Market was worth
US$ 48 Billion in 2020.

• And is expected to grow at a rate of 6.0%

(@ CAGR) from 2021 to 2027, reaching
US$ ~88 Billion in 2027.

Courtesy: maximizemarketresearch.com
 SO WHAT?
• India Govt approved a Rs. 76,000-crore scheme to boost semiconductor and display manufacturing in
the country to position India as global hub for hi-tech production, and attract large chip makers.
https://www.indiatoday.in/india/story/govt-clears-rs-76-000-crore-scheme-to-boost-semiconductor-dis
play-manufacturing-1888302-2021-12-15

• Karnataka Government signed a MoU with Israel-based ISMC Analog Fab Pat Ltd for setting up such a
plant with an investment of Rs 22,900 crore($3 Billion)
https://www.newindianexpress.com/states/karnataka/2022/may/02/mysuru-to-get-rs-23000-crorechip-
fab-plant-2448701.html (Dated 2nd May, 2022.)
 What’s in There for ME?
• What YOU need in India to match a
$100K life style of US

Courtesy:
https://www.reddit.com/r/IndiaSpeaks/comments/vzjjm7/next
_time_your_cousin_who_has_settled_in_the_us/
What’s a CHIP and how are they made?

• This is CHIP ==>

• And its quite a

history …
 …Its all started…
• In 1947, when John Baden, William Shockley and Watter Brattain of Bell Labs unveiled the first
functioning point contact Germenium transistor.

• In 1958, Jack Kilby of TI built first Integrated Circuit with two BJTs connected on single piece of
silicon.

• In 1963, Frank Wanlass and C.T.Sah of Fairchild unveiled the first logic gate in Complementary
symmetric circuit configuration(CMOS).

• Early ICs used NMOS technology for its obvious advantages over PMOS and then CMOS took over the
Fabrication Process.
Evolution of ICs :
 Structure of an NMOS

• The 3D figure depicts the NMOS

transistor’s structure over p-
substrate(body/bulk).
• On the top center of the device a low-
resistivity electrode, separated by an
insulator(SiO2) from the body, is formed
with heavily doped n/ptype poly-
silicons(Gate).
• By implanting heavily doped donar(n+)
impurities, source and drain are formed.
 Fabrication Process :
Employs three kinds of materials based on their conducting properties.

• Conductors – such as Silver, Gold, Copper, Aluminum, Bismuth, etc. for electrical connectivity and Metal
Resistors.

• Insulators – such as SiO2 for isolating conducting/semi-conducting materials from each other in MOS
devices and Capacitors.

• Semi-Conductors – such as Silicon, GaAs for forming p/n diffusions and impalnts.
 Fabrication Process : Sequence
• Silicon Wafer Processing
• Oxidation
• Photo-Lithography
• Chemical Vapor Deposition
• Etching
• Diffusion & Ion Implantation
• Metallization and
• Packaging
 Silicon Wafer Processing
• Pure, Single-crystal silicon melted is at 14000 C
and a seed contained desired crystal orientation is
inserted into molten silicon and slowly pulled
out(1mm/min) to form a ingot with a diameter of
8-12 inches.
• It is sliced into 0.5-0.75mm thick disks called
Wafers.
 Oxidation
• A thin film of SiO2 is formed when silicon
reacts with Oxygen[Gas-in Dry
Oxidation/Steam-in Wet Oxidation] at 1000o C
to 1200o C.

• This thermally grown layer has excellent

insulation properties and serves as mask to
restrict the impurities whilst doping over non-
oxidized/etched silicon regions.
 Photo-Lithography
• Wafer Surface is coated with the Photoresist
using a spin-on technique.
• Then, a Photographic plate with drawn
patterns(Mask) is used to selectively expose the
photoresist under UV rays.

• Depending on the type of photoresist (+ve/-ve),

the exposed or unexposed parts become
vulnerable to certain chemical solvents.
• Eg: For +ve Photoresist the exposed areas are
softened
 Chemical Vapor Deposition
• Thin SiO2 (typically of 0.1um) is grown over the
wafer and then heavily doped Polysilicon is
deposited by CVD.

• In CVD, gases or vapors are chemically reacted

forming solids on a substrate forming desired
solid-state areas.
 Etching
• Once the desired shape is patterned, the etching
process allows unprotected areas to be removed
either by :

– Chemicals [Wet Etching] or by

– Ionized gases [Dry or Plasma Etching]
 Diffusion & Ion Implantation
• Dopants are added to change the electrical
characteristics of silicon locally through:

– Diffusion: Dopants deposited on silicon move

through the lattice by thermal diffusion to form
Well areas.

– Ion Implementation: Highly energized donor

or acceptor atoms impinge onto the surface and
travel below it to form Source/Drain areas
 Metallization
• The metal layer, for inter-connecting various
components, is normally deposited either by
sputtering or vaporization process and
unwanted metal areas can be etched out.

• The metal film thickness can be controlled by

the length of the sputtering/vaporizing time.
 Packaging
• The finished silicon wafer, containing several hundreds of
chips and circuits, are first tested electrically(test chip or
test vehicle).

• Individual Circuits/Chips are then separated by Dicing

and are mounted in packages.

• Finally, the package is sealed using plastic or epoxy under

vacuum or in an inert atmosphere.
 Silicon Over Insulator
• A Buried Oxide[BOX] layer isolating the body
from substrate is grown in the oxidation phase
itself.

• Thus, an SOI wafer consists of 3 layers, viz: Thin

Top Silicon
Buried Oxide and
Substrate
 Buried Oxide[BOX] Layer
• BOX reduces the parasitic junction
capacitance improving switching
speed of the transistor.

• The Body Biasing, along with BOX

layer forms a virtual back-gate.
 Advantages of SOI Process
• Also, BOX minimizes the unwanted leakage paths which results in low power consumption compared to
Bulk-MOS transistor.
 Back-Gate Biasing
• Based on the potentials applied on the Gate and Back-gate, SOI transistor can be operated either for
high-performance or for low-power consuming applications.
 FinFet
• Former TSMC CTO and Berkeley Professor
Chenming Hu presented the concept of FinFet
proposing Gate controlling the channel from more
than one side.

• Modern finfets are tri-gate structures where the

Gate is wrapped around the channel.

• In bulk/planar-MOS the channel is horizontal

plane, where in FinFet its vertical.
 FinFet (Continued..)
• So, the height of the fin determines the width of the channel.

• Width of the Channel = (2 x Fin Height) + Fin Width

• Since, the effective device width is quantized in multiples of

Fin Height and limiting the choice of arbitrary channel width
as in Planar-MOS.
 FinFet (Continued....)
• The drive current in Finfet can further be
increased by increasing either the Fin’s height or
the number of parallel fins.

• Thus, they provide very good electrostatic

control of the channel.

• Reduces the short channel effects.

 Gate All Around FET
• The Channel will entirely be surrounded by the GATE resulting 4-active regions per channel.

• This Process is extremely sophisticated involving more number of Fabrication Steps.

 VLSI Streams/Domains:
• Digital{ Logic Cells & Memory Cells}
• Front End => Logic Design/Verilog Design(System Verilog)
• Middle End => System Verification(RTL, DFT, etc)
• Back End => Physical Design

• Analog{IO, RF, Analog & Mixed Signal, Logic Cells & Memory Cells}
• Circuit/Schematic Design
• Layout/Mask Design
VLSI Streams/Domains(Contd):
 Feasibility Study:
• Planar-MOS libraries can easily be translated to SOI and it employs almost same infrastructure.

• Both SOI and Finfet process technologies have been sustaining across the FABs that could adopt to
either or both of them.

• SOI Process can be adopted along with FinFet to form SOI-Finfets which significantly increases the
Cost-per-unit.

• GAA Devies can be realized with NanoWire Channels and NanoSheet Channels
 Bibliography
• http://www.chipex.co.il/_Uploads/dbsAttachedFiles/ChipExAMAT.pdf
• Basic VLSI Design by Douglas Pucknell & Kamran Eshraghian
• http://www-micro.deis.unibo.it/~masetti/Dida01
• https://global.oup.com/us/companion.websites/fdscontent/uscompanion/us/static/companion.websites/
9780199339136/Appendices/Appendix_A.pdf
• http://www.vlsi-expert.com
THANK YOU