Flip Flops

Unit 4
Sequential circuit
Compiled by: Pallavi Vyas

Combinational Logic
• The outputs depend only on the state of the inputs all of the
time. Any change in the state of one of the inputs will ripple
through the circuit immediately.
o Examples of combinational logic are NAND and NOR gates,
Inverters, and Buffers. These four logic gates form the basis
of almost all combinational logic circuits as well as flip flops.
• Circuits that change the state of the output in this manner are
also known as asynchronous circuits.
o However, not all asynchronous circuits are combinational
logic circuits.

Sequential Logic
• Has memory; the circuit stores the result of
the previous set of inputs. The current output
depends on inputs in the past as well as
present inputs.
o The basic element in sequential logic is the
bistable latch or flip-flop, which acts as a memory
element for one bit of data.

Clocked Circuits
• Most flip-flops are clocked so that the output change state
based upon the state of the inputs at precisely
determined times.
o Usage varies — in this course, ‘flip-flops’ will be used for
clocked circuits and ‘latches’ for circuits that are
asynchronous.
• A common clock used in many flip-flips in one circuit ensures

that all parts of a digital system change state at the same time.
This is called a synchronous system

Bistable Circuit
• At the heart of a bistable circuit is a pair of
inverters connected in a loop — with
feedback, in other words. It has two stable
states.
– Without some control, there isn’t a way to force

the bistable circuit into one or the other state.
Bistable Circuits
•The bistable circuit is used as a ‘bus keeper’ to
hold a node at a definite 1 or 0. It is also the heart
of a ‘static random access memory’ (SRAM) cell.
o Similar operation occurs for any ring composed of an
even number of invertors.
o What would happen if 3 inverters (or larger odd
number) are connected in series?
 This type of circuit is called a ring oscillator.
 Check this out in the laboratory or in PSpice!

Latch
Latch- A latch (bistable multivibrator) is a device
which has two stable states namely high output
as well as low-output. This includes a feedback
lane; accordingly, data can be stored with the
device. A latch is a memory device used to store
one bit of data. These are same like flip-flops,
however, they are not synchronous devices.
They do not work on edges of the clock as FFs
do.
Flip Flops
• A Flip-Flop or FF is a couple of latches, and the
designing of this can be done using a NOR gate
or a NAND gate. Therefore, an FF can have 2-
inputs, 2-outputs, a set as well as reset. This
type of FF is named as SR-FF. The main
function of the flip-flop is to store the binary
values. A Flip-Flop will have an extra CLK
signal to make it work in a different way when
contrasted with a latch.
Sequential Circuits
Circuits that we Information Storing
have learned Circuits
so far
Timed “States”

Sequential Logic: Concept
• Sequential Logic circuits remember past inputs
and past circuit state.
• Outputs from the system are
“fed back” as new inputs
• The storage elements are circuits that are
capable of storing binary information:
memory.

Types of Flip Flops
• S-R Flip Flop
• D Flip Flop
• J-K flip flop
• T flip flop

S (set)-R(reset) Latch
S R Q
0 0 No change
0 1 0
1 0 1
1 1 Race condition

Working of S-R
Case1:
- Let us assume S=0,R=0 and Q=0 (No change output – 0)
- Let us assume S=0,R=0 and Q=1 (No change output – 1)
Case2:
- Let us assume S=0,R=1 and Q=0 (Reset output – 0)
- Let us assume S=0,R=1 and Q=1 (Reset output – 0)
Case3:
-Let us assume S=1,R=0 and Q=0 (set output – 1)
-Let us assume S=1,R=0 and Q=1 (set output – 1)
Case4:
-Let us assume S=1,R=1 and Q=0 (Race condition)
-Let us assume S=1,R=1 and Q=1(Race condition)
https://youtu.be/OyEYA8kNFZM - for working of S-R latch

S-R Flip Flop
• S-R Flip Flop:
S R Q
• Truth Table:
0 0 No change
0 1 0
1 0 1
1 1 Race condition

State diagram

Application or Excitation table for S-R Flip
Flop

D (Delay) Flip Flop
• Truth Table:
D Q
0 0
1 1

Present and next state table

State Diagram

Application or Excitation table for D Flip
Flop
Q(t) Q(t+1) D
0 0 0
0 1 1
1 0 0
1 1 1

J-K Flip Flop
• Truth Table: J K Q
0 0 No change
0 1 0
1 0 1
1 1 Q’ (Toggle)

Application or Excitation table for J-K Flip
Flop
Q(t) Q(t+1) J K
0 0 0 x
0 1 1 x
1 0 x 1
1 1 x 0

T (Toggle) flip flop
T Q
0 Qn
1 Qn’


State Diagram

Application or Excitation table for T Flip
Flop
Q(t) Q(t+1) T
0 0 0
0 1 1
1 0 1
1 1 0

Analysis of Sequential Circuits
• The behaviour of a sequential circuit is
determined from the inputs, the outputs and
the states of its flip-flops. Both the output and
the next state are a function of the inputs and
the present state.

• We start with the logic schematic from which we can
derive excitation equations for each flip-flop input.
Then, to obtain next-state equations, we insert the
excitation equations into the characteristic equations.
The output equations can be derived from the
schematic, and once we have our output and next-
state equations, we can generate the next-state and
output tables as well as state diagrams. When we
reach this stage, we use either the table or the state
diagram to develop a timing diagram which can be
verified through simulation.
Design of Sequential Circuits
• The design of a synchronous sequential circuit starts from a set of
specifications and culminates in a logic diagram or a list of Boolean
functions from which a logic diagram can be obtained. In contrast
to a combinational logic, which is fully specified by a truth table, a
sequential circuit requires a state table for its specification. The first
step in the design of sequential circuits is to obtain a state table or
an equivalence representation, such as a state diagram.
• A synchronous sequential circuit is made up of flip-flops and
combinational gates. The design of the circuit consists of choosing
the flip-flops and then finding the combinational structure which,
together with the flip-flops, produces a circuit that fulfils the
required specifications. The number of flip-flops is determined
from the number of states needed in the circuit.

Design of Sequential Circuits
• Example : We wish to design a synchronous
sequential circuit whose state diagram is
shown in Figure.

From the state diagram, we can generate the state table shown in Table1 . Note that
there is no output section for this circuit. Two flip-flops are needed to represent the
four states and are designated Q0Q1. The input variable is labelled x.

We shall now derive the excitation table2 and the combinational
structure .

The table is now arranged in a different form shown in below Table3 where
the present state and input variables are arranged in the form of a truth
table. Remember, the excitable for the JK flip-flop was derive in Table 1.

• In the first row of Table 3, we have a transition for flip-flop
Q0 from 0 in the present state to 0 in the next state.
• In Table 1 we find that a transition of states from 0 to 0
requires that input J = 0 and input K = X. So 0 and X are
copied in the first row under J0 and K0 respectively.
• Since the first row also shows a transition for the flip-flop
Q1 from 0 in the present state to 0 in the next state, 0 and X
are copied in the first row under J1 and K1.
• This process is continued for each row of the table and for
each flip-flop, with the input conditions as specified in Table
2
The simplified Boolean functions for the combinational circuit can now be
derived. The input variables are Q0, Q1, and x; the output are the variables J0,
K0, J1 and K1. The information from the truth table is plotted on the Karnaugh
maps shown in the Figure.

The flip-flop input functions are derived.
Note: the symbol ¤ is exclusive-NOR.
J0 = Q1 * x' K0 = Q 1 * x
J1 = x K1 = Q0' * x' + Q0 * x = Q0 ¤ x

State Reduction
• Any design process must consider the problem of
minimizing the cost of the final circuit. The two most
obvious cost reductions are reductions in the
number of flip-flops and the number of gates.
• The number of states in a sequential circuit is closely
related to the complexity of the resulting circuit. It is
therefore desirable to know when two or more
states are equivalent in all aspects. The process of
eliminating the equivalent or redundant states from
a state table/diagram is known as state reduction.
Example: Let us consider the state table of a sequential circuit
shown in Table 1.

It can be seen from the table that the present state A and F both have the same next states, B (when x=0) and C (when x=1). They also produce the same output 1 (when x=0) and 0 (when x=1). Therefore states A and
F are equivalent. Thus one of the states, A or F can be removed from the state table. For example, if we remove row F from the table and replace all F's by A's in the columns, the state table is modified as shown in
Table 2

It is apparent that states B and E are equivalent. Removing E and
replacing E's by B's results in the reduce table shown in Table 3.

• The removal of equivalent states has reduced
the number of states in the circuit from six to
four. Two states are considered to
be equivalent if and only if for every input
sequence the circuit produces the same
output sequence irrespective of which one of
the two states is the starting state.

Counter
• A sequential circuit that goes through a prescribed sequence of
states upon the application of input pulses is called a counter. The
input pulses, called count pulses, may be clock pulses. In a counter,
the sequence of states may follow a binary count or any other
sequence of states. Counters are found in almost all equipment
containing digital logic. They are used for counting the number of
occurrences of an even and are useful for generating timing
sequences to control operations in a digital system.
• Of the various sequences a counter may follow, the straight binary
sequence is the simplest and most straight forward. A counter that
follows the binary sequence is called a binary counter. An n-bit
binary counter consists of n flip-flops and can count in binary from
0 to 2n - 1.

Introduction
• Counter is a circuit which cycle through state
sequence
• Two types of counter
– Synchronous counter (e.g. parallel)
– Asynchronous counter (e.g. ripple)
• Ripple counter let some flip-flop output to be used as
clock signal source for other flip-flop
• Synchronous counter use the same clock signal for all
flip-flop

Asynchronous Counter (Ripple)
• Asynchronous Counter : flip-flop doesn’t
change condition simultaneously because it
doesn’t use single clock signal
• Also known as ripple counter because clock
signal input as ripple through counter.
• Asynchronous counters are also called ripple-counters because of the way
the clock pulse ripples it way through the flip-flops.

Synchronous Counter (Parallel)
• Synchronous counter: flip-flop with the same
synchronous clock signal
• We can build synchronous counter using
process to design sequential circuit
• Example: 2-bit synchronous binary counter
(using T flip-flop or JK)

Design of Counter
• A counter is first described by a state diagram,
which is shows the sequence of states through
which the counter advances when it is
clocked. Figure 1 shows a state diagram of a 3-
bit binary counter.

• The circuit has no inputs other than the clock
pulse and no outputs other than its internal
state (outputs are taken off each flip-flop in
the counter). The next state of the counter
depends entirely on its present state, and the
state transition occurs every time the clock
pulse occurs. Figure 1 shows the sequences of
count after each clock pulse.

Truth Table

Since there are eight states, the number of flip-flops required would be three.
Now we want to implement the counter design using JK flip-flops.
Next step is to develop an excitation table from the state table, which is
shown in Table 2.

Now transfer the JK states of the flip-flop inputs from the
excitation table to Karnaugh maps to derive a simplified Boolean
expression for each flip-flop input. This is shown in Figure.

The 1s in the Karnaugh maps of Figure 2 are grouped with "don't
cares" and the following expressions for the J and K inputs of
each flip-flop are obtained:
J0 = K 0 = 1
J1 = K 1 = Q 0
J2 = K 2 = Q 1 * Q 0

Counter Example2
• Design a 3 bit counter using T flip-flops. The
state diagram is shown here again in next
slide.

Excitation table

transfer the flip-flop input functions to Karnaugh maps to derive a
simplified Boolean expressions

Finally, draw the logic diagram of the circuit from the expressions obtained. The
complete logic diagram of the counter is shown in Figure

Modules n counter
 n flip-flops  a MOD (modulus) 2 counter. n
(Note: A MOD-x counter cycles through x

states.)
 Output of the last flip-flop (MSB) divides the
input clock frequency by the MOD number of
the counter, hence a counter is also a
frequency divider.

Mod-6 counter
111 000
Temporary 001
state
110 010
101 011
100

Introduction: Registers
 An n-bit register has a group of n flip-flops and some
logic gates and is capable of storing n bits of
information.
 The flip-flops store the information while the gates
control when and how new information is transferred
into the register.
 Some functions of register:
 retrieve data from register
 store/load new data into register (serial or parallel)
 shift the data within register (left or right)
Simple Registers
 No external gates.
 Example: A 4-bit register. A new 4-bit data is
loaded every clock cycle.
A3 A2 A1 A0
Q Q Q Q
D D D D
CP
I3 I2 I1 I0

Registers With Parallel Load
 Instead of loading the register at every clock
pulse, we may want to control when to load.
 Loading a register: transfer new information
into the register. Requires a load control
input.
 Sequential load: transfer one bit at a time.
 Parallel loading: all bits are loaded
simultaneously
Shift Registers
 Another function of a register, besides
storage, is to provide for data movements.
 Each stage (flip-flop) in a shift register
represents one bit of storage, and the shifting
capability of a register permits the movement
of data from stage to stage within the register,
or into or out of the register upon application
of clock pulses.

Different types of Shift Registers
• Serial-in to Serial-out (SISO) - the data is shifted serially “IN”
and “OUT” of the register, one bit at a time in either a left or
right direction under clock control.
• Serial-in to Parallel-out (SIPO) - the register is loaded with
serial data, one bit at a time, with the stored data being
available at the output in parallel form.
• Parallel-in to Serial-out (PISO) - the parallel data is loaded into
the register simultaneously and is shifted out of the register
serially one bit at a time under clock control.
• Parallel-in to Parallel-out (PIPO) - the parallel data is loaded
simultaneously into the register, and transferred together to
their respective outputs by the same clock pulse.
Shift Registers
 Basic data movement in shift registers (four bits are
used for illustration).
Data in Data out Data out Data in
(a) Serial in/shift right/serial out (b) Serial in/shift left/serial out
Data in Data in
Data in
Data out
Data out
(c) Parallel in/serial out (d) Serial in/parallel out
Data out
(e) Parallel in /
parallel out
(f) Rotate right (g) Rotate left

Serial In/Serial Out Shift Registers
 Accepts data serially – one bit at a time – and also
produces output serially.
Serial data Q0 Q1 Q2 Q3 Serial data

D Q D Q D Q D Q
input output
C C C C
CLK
Serial In/Parallel Out Shift Registers
 Accepts data serially.
 Outputs of all stages are available simultaneously.
Data input D Q D Q D Q D Q
C C C C
CLK
Q0 Q1 Q2 Q3
Data input D SRG 4

Logic symbol
CLK C
Q0 Q1 Q2 Q3
68
Parallel In/Serial Out Shift Registers
 Bits are entered simultaneously, but output is serial.
69
Parallel In/Parallel Out Shift Registers
 Simultaneous input and output of all data bits.
Parallel In/Parallel Out Shift

CS1104-13 70
Registers
Application of a shift register
• Time Delay
• Ring counter
• Multiplier
• Divider
• Serial to parallel converter
• Parallel to serial converter
• https://www.electronics-tutorials.ws/sequenti
al/seq_5.html Compiled by: Pallavi Vyas

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Unit 4

Compiled by: Pallavi Vyas

Compiled by: Pallavi Vyas

Compiled by: Pallavi Vyas

• A common clock used in many flip-flips in one circuit ensures

Compiled by: Pallavi Vyas

– Without some control, there isn’t a way to force

Compiled by: Pallavi Vyas

Compiled by: Pallavi Vyas

Compiled by: Pallavi Vyas

Compiled by: Pallavi Vyas

Compiled by: Pallavi Vyas

https://youtu.be/OyEYA8kNFZM - for working of S-R latch

Compiled by: Pallavi Vyas

Compiled by: Pallavi Vyas

Compiled by: Pallavi Vyas

Compiled by: Pallavi Vyas

Compiled by: Pallavi Vyas

Compiled by: Pallavi Vyas

Compiled by: Pallavi Vyas

Compiled by: Pallavi Vyas

Compiled by: Pallavi Vyas

Compiled by: Pallavi Vyas

Compiled by: Pallavi Vyas

Compiled by: Pallavi Vyas

Compiled by: Pallavi Vyas

Compiled by: Pallavi Vyas

Compiled by: Pallavi Vyas

Compiled by: Pallavi Vyas

Compiled by: Pallavi Vyas

Compiled by: Pallavi Vyas

Compiled by: Pallavi Vyas

Compiled by: Pallavi Vyas

Note: the symbol ¤ is exclusive-NOR.

Compiled by: Pallavi Vyas

Compiled by: Pallavi Vyas

Compiled by: Pallavi Vyas

Compiled by: Pallavi Vyas

Compiled by: Pallavi Vyas

Compiled by: Pallavi Vyas

Compiled by: Pallavi Vyas

Compiled by: Pallavi Vyas

Compiled by: Pallavi Vyas

Compiled by: Pallavi Vyas

Compiled by: Pallavi Vyas

Compiled by: Pallavi Vyas

Compiled by: Pallavi Vyas

Compiled by: Pallavi Vyas

Compiled by: Pallavi Vyas

Compiled by: Pallavi Vyas

Compiled by: Pallavi Vyas

Compiled by: Pallavi Vyas

Compiled by: Pallavi Vyas

(Note: A MOD-x counter cycles through x

Compiled by: Pallavi Vyas

Compiled by: Pallavi Vyas

Compiled by: Pallavi Vyas

Compiled by: Pallavi Vyas

(f) Rotate right (g) Rotate left

Serial data Q0 Q1 Q2 Q3 Serial data

Data input D SRG 4

Parallel In/Parallel Out Shift

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