Making Transistors

CMOS Process
1.Define well areas and transistor regions.
The first set of photolithographic steps is used to
specify the areas in which the transistors will be
fabricated.
NMOS devices are diffused in a p-type well.
PMOS devices are diffused into an n-type well.
In recent technologies, twin tubs are used, meaning
that an n-well and a p-well are separately diffused into
a common substrate.
The transistor areas defined within the well areas are
separated from one another using shallow trench
isolation (STI).
The “trenches” are dug out of the silicon in regions
between transistors, and oxide is deposited in these
trenches using a chemical vapor deposition process
(CVD).
2.Define gate region
The second set of lithographic steps defines the desired
patterns for gate electrodes.
In a 0.13 μm process, a clean thermal oxide about 22 A°
thickness is grown in the transistor areas by exposure to
oxygen in a furnace.
This thin gate oxide is the insulator in the MOS structure.
Threshold adjustment implants are applied to the gate
regions to achieve the desired VT values for PMOS and
NMOS devices.
3.Define poly gate:
Another CVD process deposits a layer of
polycrystalline silicon (poly) over the entire wafer.
Undesired poly and the underlying thin oxide are
removed by chemical etching thus producing a self-
aligned gate node.
The term “self-aligned” refers to the fact that the
source and drain regions will automatically align with
the poly gate if the gate is placed down first.
4.Form source/drain regions. (PMOS)
A p+ dopant (boron) is introduced into the n-well to
form the p-channel transistor source and drain.
 Ion implantation is used for each doping step.
(NMOS)
Then an n+ dopant (phosphorus or arsenic) is
introduced into the p-well that will become the n-
channel transistor source and drain.
P-Well N-Well
5.Deposit silicide material.
The source, drain, and gate materials have relatively
high resistance that may slow down the operation of
the transistor.
 To reduce the resistance, a silicide material is
deposited onto the source, drain, and poly regions.

6.The masking step also defines the areas in which

contacts to the transistors are to be made.
Self-aligned silicides are often called salicides
Silicide formed over Polysilicon is called as Polycide
Deep submicron CMOS transistor structure

STI-Shallow Trench Isolation

Making Wires
Wires to connect the transistors.
These connections, primarily done using a metal such
as Al or Cu, are commonly known as interconnect.
In the early generations of MOS technology, only one
or two metal layers were available to wire up the
devices.
 Since there were only a few thousands devices to
connect, the wiring process was rather
straightforward.
The number of layers of interconnect has grown over
the past 25 years from one layer to over eight layers.
The fabrication of interconnect begins with the
first metal layer that is used to make contact with
transistor source, drain, and gate terminals
and to connect them to nearby VDD,Gnd
and inputs/outputs of other transistors.
Initially, a layer of insulating material is applied and
then polished to a flat surface.
Next, contact holes are etched into the insulator and
filled with a conducting material such as tungsten.
The metal material (either aluminum or copper) is
then applied to the surface and patterned to form the
desired wires.