Verilog Data Types

The several data types are nets, registers, vectors, integer, real,
parameters and arrays.
Nets:
It is declared by the predefined word wire.
Nets have values that change continuously by the circuits that are
driving them.
Verilog Data Types
• Nets:
It is declared by the predefined word wire.
It supports 4 values
Example:
Value Definition
0 Logic 0 (false)
wire sum;
1 Logic 1 (true) wire S1 = 1’b0;
X unknown
z High impedance
Verilog Data Types
Registers:
• It store values until they are updated.
• It is a data storage elements.
• It is declared by the predefined word reg.
• It supports 4 values of register.
Value Definition
0 Logic 0 (false)
1 Logic 1 (true)
X unknown
z High impedance
 Verilog Data Types
• Vectors:
• Vectors are multiple bits
• Register or net can be declared as a vector
• Vectors are declared by brackets
Examples:
Wire [3:0]a=4’b1010;
Reg[7:0]total=8’d12;
Verilog Data Types
Integers:
• It is defined by a predefined word integer.
Real:
• Real (floating-point) numbers are declared with predefined word real.
• Example:
1. 2.4,56.3 and 5e12(5*10^12)
 Verilog Data Types
• Vectors:
• Vectors are multiple bits.
• A register or a net can be declared as a vector.
• Vectors are declared by brackets [ ].
• Example:
• Wire [3:0] a = 4’b1010
• Reg [ 7: 0] total = 8’d12;
• First statement declares the net a. It has 4 bits and the values are
1010
 Verilog Data Types
Parameters:
• It represents the global constants.
• It is declared by the predefined word parameter.
• Example:
Module compr(X,Y,Xgty,Xlty,Xegy)
Parameter N=3;
Input [N:0] X,Y;
Output Xgty,Xlty,Xegy;
Wire [N:0] sum, yb;
 Verilog Data Types
• Arrays:
• Registers and integers can be written as arrays.
Example:
parameter N=4;
parameter N=3;
reg signed [M:0] carry [0:N];
reg [M:0] b [0:N];
integer sum [0:N];
Example 1
Example 2
Example 3
Highlights of Dataflow Description
• Data flow is one type of hardware description.
• Other types are behavioral, structural (gate) level, switch level, mixed
level
• It simulate the system by showing how the signal flows from system
inputs to outputs.
• Signal assignment statement are concurrent.
• At any simulation time, all signal-assignment statements that have an
event are executed concurrently.
Structure of the Data-flow Description
 Signal Declaration and Assignment
Statements
• Signals a,b,c,d are inputs.
• Signal y is the output.
• Signals s1 and s2 are intermediates
, using a predefined word wire.
• All the ports in the Verilog are
defined by wire.
• The values will change when the
system drives it
Signal Declaration and Assignment
Statements
• Another type of declaration in Verilog is register, where the values need to
be stored.
• Hence, a signal assignment statement is used to assign a value to the signal.
• The execution is done in two ways
• Calculation
• O1 = I1 & I2 (1&1 =1), at time t0
• Assignment
• Delay time is specified as #10;
• If delay time is not specified , a default small delay time in terms of
seconds is specified.
• Since is small , it cannot be seen
Concurrent signal-assignment statements
• When both the inputs I1 and I2 are executed concurrently without
any delay.
• It means o1 and o2 are values are done at the same time T0.
Constant Declaration and Assignment
Statements
• A constant is declared by the type time or integer.
• Example:
• Time period;
• Period = 100;
Example 1
Assigning a Delay time to the Signal-
Assignment Statement.
Module 5