VHDL 강좌 m10 - 23

Basic VHDL
RASSP Education & Facilitation

Module 10
Version 2.02
Copyright  1995-1998 RASSP E&F
All rights reserved. This information is copyrighted by the RASSP E&F Program
and may only be used for non-commercial educational purposes. Any other use of
this information without the express written permission of the RASSP E&F Program
is prohibited. All information contained herein may be duplicated for non-
commercial educational use provided this copyright notice is included. No warranty
of any kind is provided or implied, nor is any liability accepted regardless of use.
FEEDBACK:
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feedback@rassp.scra.org or
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RASSP Roadmap RASSP
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RASSP DESIGN LIBRARIES AND DATABASE

Primarily Primarily
software
VIRTUAL PROTOTYPE hardware
HW HW
DESIGN FAB
SYSTEM FUNCTION HW & INTEG.
DEF. DESIGN SW & TEST
PART.
SW SW
HW & SW
DESIGN CODE
CODESIGN
VHDL
VHDL
Module Goals RASSP
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 Introduce basic VHDL constructs
 Introduce the VHDL simulation cycle and timing

model
 Illustrate VHDL’s utility as a digital hardware

description language

Module Outline RASSP
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 Introduction
 VHDL Design Example
 VHDL Model Components
 Entity Declarations
 Architecture Descriptions
 Timing Model

Module Outline (Cont.) RASSP
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 Basic VHDL Constructs

 Data types
 Objects
 Sequential and concurrent statements
 Packages and libraries
 Attributes
 Predefined operators
 Examples
 Summary

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 Introduction
 Examples
 Summary

VHDL Education Coverage RASSP
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 In a survey of 71 US universities (representing

about half of the EE graduating seniors in 1993),
they reported
 44% have no training on or use of VHDL in any
undergraduate EE course
 45% have no faculty members who can teach VHDL
 14% of the graduating seniors have a working
knowledge of VHDL and only 8% know Verilog
 However, in the 1994 USE/DA Standards Survey,
85% of the engineers surveyed were designers
and reported
 55% were familiar with EDIF
 55% were familiar with VHDL
 33% were familiar with Verilog

Reasons for Using VHDL RASSP
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 VHDL is an international IEEE standard

specification language (IEEE 1076-1993) for
describing digital hardware used by industry
worldwide
 VHDL is an acronym for VHSIC (Very High Speed
Integrated Circuit) Hardware Description Language
 VHDL enables hardware modeling from the gate

to system level
 VHDL provides a mechanism for digital design

and reusable design documentation

VHDL’s History RASSP
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 Very High Speed Integrated Circuit (VHSIC)

Program
 Launched in 1980
 Aggressive effort to advance state of the art
 Object was to achieve significant gains in VLSI
technology
 Need for common descriptive language
 $17 Million for direct VHDL development
 $16 Million for VHDL design tools
 Woods Hole Workshop

 Held in June 1981 in Massachusetts
 Discussion of VHSIC goals
 Comprised of members of industry, government, and
academia
VHDL’s History (Cont.) RASSP
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 In July 1983, a team of Intermetrics, IBM and

Texas Instruments were awarded a contract to
develop VHDL
 In August 1985, the final version of the language
under government contract was released: VHDL
Version 7.2
 In December 1987, VHDL became IEEE Standard
1076-1987 and in 1988 an ANSI standard
 In September 1993, VHDL was restandardized to
clarify and enhance the language
 VHDL has been accepted as a Draft International
Standard by the IEC

Gajski and Kuhn’s Y Chart RASSP
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Architectural Structural
Behavioral
Algorithmic
Processor
Systems Functional Block
Hardware Modules
Algorithms Logic
ALUs, Registers
Register Transfer
Circuit Gates, FFs
Logic
Transfer Functions Transistors
Rectangles
Cell, Module Plans
Floor Plans
Clusters
Physical Partitions
Physical/Geometry
Representation of a
RASSP System RASSP
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Independently Describe: 1) Resolution of INTERNAL (kernel) details

2) Representation of EXTERNAL (Interface) details
In terms of:
Temporal Resolution
High Res. Gate Clock Cycle Instr. Cycle System Event Low Res.
Propagation (pS) (10s of nS) (10s of uS) (10s of mS)
Data Value Resolution
High Res. Bit true Value True Composite Token Low Res.
(0b01101) (13) (13,req,(2.33, j89.2)) (Blue)
Functional Resolution
High Res. All functions modeled Low Res.

Some functions not modeled
(Full-functional)
(Interface-functional)
Structural Resolution
High Res. Structural Block diagram Single block box Low Res.
Gate netlist Major blocks (No implementation info)
Programming Level (Full implementation) (Some implementation info)
High Res. Micro- Assembly HLL (Ada,C) DSP primitive Major Low Res.
code code Statements Block-oriented modes
(fmul r1,r2) (i := i+1) (FFT(a,b,c)) (Search,Track)
(Note: Low resolution of details = High level of abstraction
High resolution of details = Low level of abstraction
Copyright  1995-1998 RASSP E&F [Hein97]
Graphical Representation of
the Model Levels using the RASSP
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RASSP Taxonomy
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Symbol Key
Model resolves information at specific level
Model resolves information at any of the levels spanned,

case dependent
Model optionally resolves information at levels spanned
Model resolves partial information at levels spanned, such

as control but not data values or functionality
Model does not contain information on attribute
Virtual Prototype Internal External
Temporal
A Virtual Prototype can be constructed at Data Value
any level of abstraction and may include a Functional
mixture of levels. It can be configured
Structural
quickly and cost-effectively, and, being a
computer simulation, provides non-
SW Programming Level
invasive observability of internal states.

RASSP
RASSP Taxonomy (Cont.)

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Behavioral Level
Internal External
A behavioral model describes the function
and timing of a component without Temporal
describing a specific implementation Data Value
Functional
Structural
RTL Level
Internal External
An RTL model describes a system in terms
of registers, combinational circuitry, low- Temporal
level buses, and control circuits, usually Data Value
implemented as finite state machines
Functional
Structural

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Algorithm Level
Internal External
The algorithm level of abstraction
describes a procedure for implementing a Temporal
function as a specific sequence of Data Value
arithmetic operations, conditions, and
Functional
loops
Structural
Performance Level
Internal External
Performance models may be written at any
level of abstraction and measure system Temporal
performance associated with response Data Value
time, throughput, and utilization
Functional
Structural

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Structural Level
Internal External
A structural model represents a
component or system in terms of the Temporal
interconnections of its constituent Data Value
components.
Functional
Structural
Gate Level
Internal External
A gate-level model describes the function,
timing, and structure of a component in Temporal
terms of the structural interconnection of Data Value
boolean logic blocks
Functional
Structural

Additional Benefits of VHDL RASSP
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 Allows for various design methodologies

 Provides technology independence
 Describes a wide variety of digital hardware
 Eases communication through standard
language
 Allows for better design management
 Provides a flexible design language
 Has given rise to derivative standards :
 WAVES, VITAL, Analog VHDL
Putting It All Together RASSP
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Package
Generics Entity Ports
Architecture Architecture Architecture
Concurrent Process
Concurrent
Statements
Statements
Sequential Statements
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 Introduction

 VHDL Models of Hardware
 Examples
 Summary

VHDL Design Example RASSP
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 Problem: Design a single bit half adder with carry

and enable
 Specifications
 Inputs and outputs are each one bit
 When enable is high, result gets x plus y
 When enable is high, carry gets any carry of x plus y
 Outputs are zero when enable input is low
x
carry
y Half Adder
result
enable

VHDL Design Example
Entity Declaration RASSP
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 As a first step, the entity declaration describes

the interface of the component
 input and output ports are declared
ENTITY half_adder IS
PORT( x, y, enable: IN BIT;

carry, result: OUT BIT);
END half_adder;
x
Half carry
y
Adder result
enable

VHDL Design Example
Behavioral Specification RASSP
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 A high level description can be used to describe

the function of the adder
ARCHITECTURE half_adder_a OF half_adder IS
BEGIN
PROCESS (x, y, enable)
BEGIN
IF enable = ‘1’ THEN
result <= x XOR y;
carry <= x AND y;
ELSE
carry <= ‘0’;
result <= ‘0’;
END IF;
END PROCESS;
END half_adder_a;
 The model can then be simulated to verify

correct functionality of the component
VHDL Design Example
Data Flow Specification RASSP
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 A second method is to use logic equations to

develop a data flow description
ARCHITECTURE half_adder_b OF half_adder IS

BEGIN
carry <= enable AND (x AND y);
result <= enable AND (x XOR y);
END half_adder_b;
 Again, the model can be simulated at this level to

confirm the logic equations

VHDL Design Example
Structural Specification RASSP
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 As a third method, a structural description can

be created from predescribed components
x
y carry
enable
result
 These gates can be pulled from a library of parts

VHDL Design Example
Structural Specification (Cont.) RASSP
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ARCHITECTURE half_adder_c OF half_adder IS
COMPONENT and2
PORT (in0, in1 : IN BIT;
out0 : OUT BIT);
END COMPONENT;
COMPONENT and3
PORT (in0, in1, in2 : IN BIT;
out0 : OUT BIT);
END COMPONENT;
COMPONENT xor2
PORT (in0, in1 : IN BIT;
out0 : OUT BIT);
END COMPONENT;
FOR ALL : and2 USE ENTITY gate_lib.and2_Nty(and2_a);

FOR ALL : and3 USE ENTITY gate_lib.and3_Nty(and3_a);
FOR ALL : xor2 USE ENTITY gate_lib.xor2_Nty(xor2_a);
-- description is continued on next slide

VHDL Design Example
Structural Specification (cont.) RASSP
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-- continuing half_adder_c description
SIGNAL xor_res : BIT; -- internal signal

-- Note that other signals are already declared in entity
BEGIN
A0 : and2 PORT MAP (enable, xor_res, result);

A1 : and3 PORT MAP (x, y, enable, carry);
X0 : xor2 PORT MAP (x, y, xor_res);
END half_adder_c;

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 Introduction




 Examples
 Summary

VHDL Model Components RASSP
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 A complete VHDL component description

requires a VHDL entity and a VHDL architecture
 The entity defines a component’s interface
 The architecture defines a component’s function
 Several alternative architectures may be

developed for use with the same entity
 Three areas of description for a VHDL
component:
 Structuraldescriptions
 Behavioral descriptions
 Timing and delay descriptions

VHDL Model Components (cont.) RASSP
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 Fundamental unit for component behavior

description is the process
 Processes may be explicitly or implicitly defined and
are packaged in architectures
 Primary communication mechanism is the signal

 Process executions result in new values being
assigned to signals which are then accessible to other
processes
 Similarly, a signal may be accessed by a process in
another architecture by connecting the signal to ports
in the the entities associated with the two architectures
 Example signal assignment statement :
Output
Output <=
<= My_id
My_id ++ 10;
10;

Entity Declarations RASSP
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 The primary purpose of the entity is to declare

the signals in the component’s interface
 The interface signals are listed in the PORT clause
 In this respect, the entity is akin to the schematic
symbol for the component
 Additional entity clauses and statements will be
introduced later in this and subsequent modules
x
Half carry
y result
Adder
enable
ENTITY half_adder IS
GENERIC(prop_delay : TIME := 10 ns);
PORT( x, y, enable : IN BIT;
carry, result : OUT BIT);
END half_adder;
Entity Declarations
Port Clause RASSP
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 PORT clause declares the interface signals of the object to the

outside world
 Three parts of the PORT clause

 Name
 Mode
 Data type
PORT
PORT (signal_name
(signal_name :: mode
mode data_type);
data_type);
 Example PORT clause:
 Note port signals (i.e. ‘ports’) of the same mode and type or subtype may be
declared on the same line
PORT
PORT (( input
input :: IN
IN BIT_VECTOR(3
BIT_VECTOR(3 DOWNTO
DOWNTO 0);
0);
ready,
ready, output
output :: OUT
OUT BIT
BIT );
);

Entity Declarations
Port Clause (cont.) RASSP
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 The port mode of the interface describes the

direction in which data travels with respect to the
component
 The five available port modes are:

 In - data comes in this port and can only be read
 Out - data travels out this port
 Buffer - data may travel in either direction, but only one
signal driver may be on at any one time
 Inout - data may travel in either direction with any
number of active drivers allowed; requires a Bus
Resolution Function
 Linkage - direction of data flow is unknown

Entity Declarations
Generic Clause RASSP
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 Generics may be used for readability, maintenance

and configuration
 Generic clause syntax :
GENERIC
GENERIC (generic_name
(generic_name :: type
type [:=
[:= default_value]);
default_value]);
 If optional default_value is missing in generic clause
declaration, it must be present when component is to be
used (i.e. instantiated)
 Generic clause example :
GENERIC
GENERIC (My_ID
(My_ID :: INTEGER
INTEGER :=
:= 37);
37);
 The generic My_ID, with a default value of 37, can be

referenced by any architecture of the entity with this
generic clause
 The default can be overridden at component instantiation
Architecture Bodies RASSP
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 Describe the operation of the component

 Consist of two parts :
 Declarative part -- includes necessary declarations
 e.g. type declarations, signal declarations, component
declarations, subprogram declarations
 Statement part -- includes statements that describe
organization and/or functional operation of component
 e.g. concurrent signal assignment statements, process
statements, component instantiation statements
ARCHITECTURE half_adder_d OF half_adder IS

SIGNAL xor_res : BIT; -- architecture declarative part
BEGIN -- begins architecture statement part
carry <= enable AND (x AND y);
result <= enable AND xor_res;
xor_res <= x XOR y;
END half_adder_d;
Structural Descriptions RASSP
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 Pre-defined VHDL components are instantiated and

connected together
 Structural descriptions may connect simple gates or
complex, abstract components
 VHDL provides mechanisms for supporting
hierarchical description
 VHDL provides mechanisms for describing highly
repetitive structures easily
Input Behavioral Output

Entity

Behavioral Descriptions RASSP
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 VHDL provides two styles of describing component behavior

 Data Flow: concurrent signal assignment statements
 Behavioral: processes used to describe complex behavior by means
of high-level language constructs
 e.g. variables, loops, if-then-else statements
 A behavioral model may bear little resemblance to system

implementation
 Structure not necessarily implied
Input Behavioral Output

Description

Timing Model RASSP
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 VHDL uses the following simulation cycle to model

the stimulus and response nature of digital hardware
Start
StartSimulation
Simulation
Delay
Update
UpdateSignals
Signals Execute
ExecuteProcesses
Processes
End
EndSimulation
Simulation
Delay Types RASSP
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 All VHDL signal assignment statements

prescribe an amount of time that must transpire
before the signal assumes its new value
 This prescribed delay can be in one of three
forms:
 Transport -- prescribes propagation delay only
 Inertial -- prescribes propagation delay and minimum
input pulse width
 Delta -- the default if no delay time is explicitly specified
Input Output
delay

Transport Delay RASSP
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 Transport delay must be explicitly specified

 I.e. keyword “TRANSPORT” must be used
 Signal will assume its new value after specified
delay -- TRANSPORT delay example
-- TRANSPORT delay example
Output
Output <=
<= TRANSPORT
TRANSPORT NOT
NOT Input
Input AFTER
AFTER 10
10 ns;
ns;
Input Output
Input
Output
0 5 10 15 20 25 30 35
Inertial Delay RASSP
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 Provides for specification propagation delay and

input pulse width, i.e. ‘inertia’ of output:
target
target <=
<= [REJECT
[REJECT time_expression]
time_expression] INERTIAL
INERTIAL waveform;
waveform;
 Inertial delay is default and REJECT is optional :

Output
Output <=
<= NOT
NOT Input
Input AFTER
AFTER 10
10 ns;
ns;
--
-- Propagation
Propagation delay
delay and
and minimum
minimum pulse
pulse width
width are
are 10ns
10ns
Input Output Input
Output
0 5 10 15 20 25 30 35
Inertial Delay (cont.) RASSP
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 Example of gate with ‘inertia’ smaller than

propagation delay
 e.g. Inverter with propagation delay of 10ns which
suppresses pulses shorter than 5ns
Output
Output <=
<= REJECT
REJECT 5ns
5ns INERTIAL
INERTIAL NOT
NOT Input
Input AFTER
AFTER 10ns;
10ns;
Input
Output
0 5 10 15 20 25 30 35
 Note: the REJECT feature is new to VHDL 1076-1993

Delta Delay RASSP
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 Default signal assignment propagation delay if

no delay is explicitly prescribed
 VHDL signal assignments do not take place
immediately
 Delta is an infinitesimal VHDL time unit so that all signal
assignments can result in signals assuming their
values at a future time
 E.g. Output
Output <=<= NOT
NOT Input;
Input;
--
-- Output
Output assumes
assumes new
new value
value in
in one
one delta
delta cycle
cycle
 Supports a model of concurrent VHDL process

execution
 Order in which processes are executed by simulator
does not affect simulation output
Delta Delay
An Example without Delta Delay RASSP
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 What is the behavior of C?

A
IN: 1->0 C
B
1 AND
ANDgate
gateevaluated
evaluatedfirst:
first:
NAND
NANDgate
gateevaluated
evaluatedfirst:
first: IN:
IN:1->0
1->0
IN:
IN:1->0
1->0 A:
A: 0->1
0->1
A:
A: 0->1
0->1 C:
C: 0->1
0->1
B:
B: 1->0
1->0 B:
B: 1->0
1->0
C:
C: 0->0
0->0
C:
C: 1->0
1->0
Delta Delay
An Example with Delta Delay RASSP
RASSP
SCRA
SCRAE&F
GT
GT UVA
E&F
UCinc
Raytheon
Raytheon
UVA
UCinc EIT
EIT ADL
ADL
What is the behavior of C?


A
IN: 1->0
C
B
1
Using
Usingdelta
deltadelay
delayscheduling
scheduling
Time Delta Event
0 ns 1 IN: 1->0
eval INVERTER
2 A: 0->1
eval NAND, AND
3 B: 1->0
C: 0->1
eval AND
4 C: 1->0
1 ns
RASSP
SCRA
SCRAE&F
GT
GT UVA
E&F
UCinc
UVA
UCinc EIT
Raytheon
Raytheon EIT ADL
ADL
 Introduction







 Examples
 Summary

Data Types RASSP
RASSP
SCRA
SCRAE&F
GT
GT UVA
E&F
UCinc
UVA
UCinc EIT
Raytheon
Raytheon EIT ADL
ADL
 All declarations of VHDL ports, signals, and variables

must specify their corresponding type or subtype
Types
Access Composite
Array Record
Scalar
Integer Real Enumerated Physical

VHDL Data Types
Scalar Types RASSP
RASSP
SCRA
SCRAE&F
GT
GT UVA
E&F
UCinc
Raytheon
Raytheon
UVA
UCinc EIT
EIT ADL
ADL
 Integer
 Minimum range for any implementation as defined by
standard: - 2,147,483,647 to 2,147,483,647
 Example assignments to a variable of type integer :
ARCHITECTURE
ARCHITECTURE test_int
test_int OFOF test
test IS
IS
BEGIN
BEGIN
PROCESS
PROCESS (X)
(X)
VARIABLE
VARIABLE a:a: INTEGER;
INTEGER;
BEGIN
BEGIN
aa :=
:= 1;
1; --
-- OK
OK
aa :=
:= -1;
-1; --
-- OK
OK
aa :=
:= 1.0;
1.0; --
-- illegal
illegal
END
END PROCESS;
PROCESS;
END
END test_int;
test_int;

VHDL Data Types
Scalar Types (Cont.) RASSP
RASSP
SCRA
SCRAE&F
GT
GT UVA
E&F
UCinc
Raytheon
Raytheon
UVA
UCinc EIT
EIT ADL
ADL
 Real
 Minimum range for any implementation as defined by
standard: -1.0E38 to 1.0E38
 Example assignments to a variable of type real :
ARCHITECTURE
ARCHITECTURE test_real
test_real OF OF test
test IS
IS
BEGIN
BEGIN
PROCESS
PROCESS (X)
(X)
VARIABLE
VARIABLE a: a: REAL;
REAL;
BEGIN
BEGIN
aa :=
:= 1.3;
1.3; ---- OK
OK
aa :=
:= -7.5;
-7.5; -- -- OK
OK
aa :=
:= 1;
1; ---- illegal
illegal
aa :=
:= 1.7E13;
1.7E13; -- -- OKOK
aa :=
:= 5.3
5.3 ns;
ns; ---- illegal
illegal
END
END PROCESS;
PROCESS;
END
END test_real;
test_real;
VHDL Data Types
RASSP
SCRA
SCRAE&F
GT
GT UVA
E&F
UCinc
Raytheon
Raytheon
UVA
UCinc EIT
EIT ADL
ADL
 Enumerated
 Userspecifies list of possible values
 Example declaration and usage of enumerated data type :
TYPE
TYPE binary
binary ISIS (( ON,
ON, OFF
OFF );
);
...
... some
some statements
statements ... ...
ARCHITECTURE
ARCHITECTURE test_enum
test_enum OF OF test
test IS
IS
BEGIN
BEGIN
PROCESS
PROCESS (X)
(X)
VARIABLE
VARIABLE a:a: binary;
binary;
BEGIN
BEGIN
aa :=
:= ON;
ON; ---- OK
OK
...
... more
more statements
statements ... ...
aa := OFF; --
:= OFF; -- OK OK
...
... more
more statements
statements ... ...
END
END PROCESS;
PROCESS;
END
END test_enum;
test_enum;
VHDL Data Types
RASSP
SCRA
SCRAE&F
GT
GT UVA
E&F
UCinc
Raytheon
Raytheon
UVA
UCinc EIT
EIT ADL
ADL
 Physical
 Require associated units
 Range must be specified
 Example of physical type declaration :
 Time is the only physical type predefined in VHDL standard
TYPE
TYPE resistance
resistance IS
IS RANGE
RANGE 00 TO
TO 10000000
10000000
UNITS
UNITS
ohm;
ohm; ---- ohm
ohm
Kohm
Kohm == 1000
1000 ohm;
ohm; --
-- i.e.
i.e. 11 K
K
Mohm
Mohm == 1000
1000 kohm;
kohm; --
-- i.e.
i.e. 11 M
M
END
END UNITS;
UNITS;

VHDL Data Types
Composite Types RASSP
RASSP
SCRA
SCRAE&F
GT
GT UVA
E&F
UCinc
Raytheon
Raytheon
UVA
UCinc EIT
EIT ADL
ADL
 Array
 Usedto group elements of the same type into a single
VHDL object
 Range may be unconstrained in declaration
 Range would then be constrained when array is used
 Example declaration for one-dimensional array (vector) :
TYPE
TYPE data_bus
data_bus IS
IS ARRAY(0
ARRAY(0 TO
TO 31)
31) OF
OF BIT;
BIT;
0 ...element indices... 31
0 ...array values... 1
VARIABLE
VARIABLE XX :: data_bus;
data_bus;
VARIABLE
VARIABLE YY :: BIT;
BIT;
YY :=
:= X(12);
X(12); --
-- YY gets
gets value
value of
of element
element at
at index
index 12
12
VHDL Data Types
Composite Types (Cont.) RASSP
RASSP
SCRA
SCRAE&F
GT
GT UVA
E&F
UCinc
Raytheon
Raytheon
UVA
UCinc EIT
EIT ADL
ADL
 Example one-dimensional array using DOWNTO :
 DOWNTO keyword must be used if leftmost index is greater than rightmost index
 e.g. ‘Big-Endian’ bit ordering
TYPE
TYPE reg_type
reg_type IS
IS ARRAY(15
ARRAY(15 DOWNTO
DOWNTO 0)
0) OF
OF BIT;
BIT;
15 ...element indices... 0
0 ...array values... 1
VARIABLE
VARIABLE XX :: reg_type;
reg_type;
VARIABLE
VARIABLE YY :: BIT;
BIT;
YY :=
:= X(4);
X(4); --
-- YY gets
gets value
value of
of element
element at
at index
index 44

VHDL Data Types
Composite Types (Cont.) RASSP
RASSP
SCRA
SCRAE&F
GT
GT UVA
E&F
UCinc
Raytheon
Raytheon
UVA
UCinc EIT
EIT ADL
ADL
 Records
 Used to group elements of possibly different types into
a single VHDL object
 Elements are indexed via field names
 Examples of record declaration and usage :
TYPE
TYPE binary
binary IS
IS (( ON,
ON, OFF
OFF );
);
TYPE
TYPE switch_info
switch_info IS IS
RECORD
RECORD
status
status :: BINARY;
BINARY;
IDnumber
IDnumber :: INTEGER;
INTEGER;
END
END RECORD;
RECORD;
VARIABLE
VARIABLE switch
switch :: switch_info;
switch_info;
switch.status
switch.status :=
:= ON;
ON; ---- status
status of
of the
the switch
switch
switch.IDnumber
switch.IDnumber :=:= 30;
30; --
-- e.g.
e.g. number
number ofof the
the switch
switch
VHDL Data Types
Access Type RASSP
RASSP
SCRA
SCRAE&F
GT
GT UVA
E&F
UCinc
Raytheon
Raytheon
UVA
UCinc EIT
EIT ADL
ADL
 Access
 Analogous to pointers in other languages
 Allows for dynamic allocation of storage
 Useful for implementing queues, fifos, etc.

VHDL Data Types
Subtypes RASSP
RASSP
SCRA
SCRAE&F
GT
GT UVA
E&F
UCinc
Raytheon
Raytheon
UVA
UCinc EIT
EIT ADL
ADL
 Subtype
 Allows for user defined constraints on a data type
 e.g. a subtype based on an unconstrained VHDL type
 May include entire range of base type
 Assignments that are out of the subtype range are illegal
 Range violation detected at run time rather than compile
time because only base type is checked at compile time
 Subtype declaration syntax :
SUBTYPE
SUBTYPE name
name IS
IS base_type
base_type RANGE
RANGE <user
<user range>;
range>;
 Subtype example :
SUBTYPE
SUBTYPE first_ten
first_ten IS
IS INTEGER
INTEGER RANGE
RANGE 00 TO
TO 9;
9;

VHDL Data Types
Summary RASSP
RASSP
SCRA
SCRAE&F
GT
GT UVA
E&F
UCinc
Raytheon
Raytheon
UVA
UCinc EIT
EIT ADL
ADL
 All declarations of VHDL ports, signals, and

variables must include their associated type or
subtype
 Three forms of VHDL data types are :
 Access -- pointers for dynamic storage allocation
 Scalar -- includes Integer, Real, Enumerated, and Physical
 Composite -- includes Array, and Record
 A set of built-in data types are defined in VHDL

standard
 User can also define own data types and subtypes

VHDL Objects RASSP
RASSP
SCRA
SCRAE&F
GT
GT UVA
E&F
UCinc
UVA
UCinc EIT
Raytheon
Raytheon EIT ADL
ADL
 There are four types of objects in VHDL

 Constants
 Variables
 Signals
 Files
 The scope of an object is as follows :

 Objects declared in a package are available to all VHDL
descriptions that use that package
 Objects declared in an entity are available to all
architectures associated with that entity
 Objects declared in an architecture are available to all
statements in that architecture
 Objects declared in a process are available only within
that process
VHDL Objects
Constants RASSP
RASSP
SCRA
SCRAE&F
GT
GT UVA
E&F
UCinc
Raytheon
Raytheon
UVA
UCinc EIT
EIT ADL
ADL
 Name assigned to a specific value of a type

 Allow for easy update and readability
 Declaration of constant may omit value so that the value assignment may be
deferred
 Facilitates reconfiguration
 Declaration syntax :
 Declaration examples :
CONSTANT
CONSTANT constant_name
constant_name :: type_name
type_name [:=
[:= value];
value];
CONSTANT
CONSTANT PI
PI :: REAL
REAL :=
:= 3.14;
3.14;
CONSTANT SPEED : INTEGER;
CONSTANT SPEED : INTEGER;
VHDL Objects
Variables RASSP
RASSP
SCRA
SCRAE&F
GT
GT UVA
E&F
UCinc
Raytheon
Raytheon
UVA
UCinc EIT
EIT ADL
ADL
 Provide convenient mechanism for local storage

 E.g. loop counters, intermediate values
 Scope is process in which they are declared
 VHDL ‘93 provides for global variables, to be discussed in the Advanced
Concepts in VHDL module
 All variable assignments take place immediately
 No delta or user specified delay is incurred
 Declaration syntax:
 Declaration examples :
VARIABLE
VARIABLE variable_name
variable_name :: type_name
type_name [:=
[:= value];
value];
VARIABLE
VARIABLE opcode
opcode :: BIT_VECTOR(3
BIT_VECTOR(3 DOWNTO
DOWNTO 0)
0) :=
:= "0000";
"0000";
VARIABLE
VARIABLE freq
freq :: INTEGER;
INTEGER;
VHDL Objects
Signals RASSP
RASSP
SCRA
SCRAE&F
GT
GT UVA
E&F
UCinc
Raytheon
Raytheon
UVA
UCinc EIT
EIT ADL
ADL
 Used for communication between VHDL components

 Real, physical signals in system often mapped to VHDL signals
 ALL VHDL signal assignments require either delta cycle or user-specified delay before
new value is assumed
 Declaration syntax :
 Declaration and assignment examples :
SIGNAL
SIGNAL signal_name
signal_name :: type_name
type_name [:=
[:= value];
value];
SIGNAL
SIGNAL brdy
brdy :: BIT;
BIT;
brdy
brdy <=
<= ‘0’
‘0’ AFTER
AFTER 5ns,
5ns, ‘1’
‘1’ AFTER
AFTER 10ns;
10ns;

Signals and Variables RASSP
RASSP
SCRA
SCRAE&F
GT
GT UVA
E&F
UCinc
UVA
UCinc EIT
Raytheon
Raytheon EIT ADL
ADL
 This example highlights the difference between

signals and variables
ARCHITECTURE
ARCHITECTURE test1
test1 OFOF mux
mux IS
IS ARCHITECTURE
ARCHITECTURE test2
test2 OFOF mux
mux IS
IS
SIGNAL
SIGNAL xx :: BIT
BIT :=
:= '1';
'1'; SIGNAL
SIGNAL yy :: BIT
BIT :=
:= '0';
'0';
SIGNAL
SIGNAL yy :: BIT
BIT :=
:= '0';
'0'; BEGIN
BEGIN
BEGIN
BEGIN PROCESS
PROCESS (in_sig,
(in_sig, y)y)
PROCESS
PROCESS (in_sig,
(in_sig, x,x, y)y) VARIABLE
VARIABLE xx :: BIT
BIT :=:= '1';
'1';
BEGIN
BEGIN BEGIN
BEGIN
xx <=
<= in_sig
in_sig XOR
XOR y;y; xx :=
:= in_sig
in_sig XOR
XOR y;
y;
yy <=
<= in_sig
in_sig XOR
XOR x;x; yy <=
<= in_sig
in_sig XOR
XOR x;
x;
END
END PROCESS;
PROCESS; END PROCESS;
END PROCESS;
END
END test1;
test1; END
END test2;
test2;
 Assuming a 1 to 0 transition on in_sig, what are

the resulting values for y in the both cases?
VHDL Objects
Signals vs Variables RASSP
RASSP
SCRA
SCRAE&F
GT
GT UVA
E&F
UCinc
Raytheon
Raytheon
UVA
UCinc EIT
EIT ADL
ADL
 A key difference between variables and signals is the

assignment delay
ARCHITECTURE
ARCHITECTURE sig_ex
sig_ex OF OF test
test IS
IS
PROCESS (a, b, c, out_1)
PROCESS (a, b, c, out_1)
BEGIN
BEGIN
out_1
out_1 <=
<= aa NAND
NAND b;
b;
out_2
out_2 <= out_1 XOR c;
<= out_1 XOR c;
END
END PROCESS;
PROCESS;
END sig_ex;
END sig_ex;
Time a b c out_1 out_2
0 0 1 1 1 0
1 1 1 1 1 0
1+d 1 1 1 0 0
1+2d 1 1 1 0 1
VHDL Objects
Signals vs Variables (Cont.) RASSP
RASSP
SCRA
SCRAE&F
GT
GT UVA
E&F
UCinc
Raytheon
Raytheon
UVA
UCinc EIT
EIT ADL
ADL
ARCHITECTURE
ARCHITECTURE var_ex
var_ex OF OF test
test IS
IS
BEGIN
BEGIN
PROCESS
PROCESS (a,
(a, b,b, c)
c)
VARIABLE
VARIABLE out_3
out_3 :: BIT;
BIT;
BEGIN
BEGIN
out_3
out_3 :=
:= aa NAND
NAND b;b;
out_4
out_4 <=
<= out_3
out_3 XOR
XOR c;c;
END
END PROCESS;
PROCESS;
END
END var_ex;
var_ex;
Time a b c out_3 out_4
0 0 1 1 1 0
1 1 1 1 0 0
1+d 1 1 1 0 1

VHDL Objects
Files SCRA
SCRA
RASSP
RASSP
E&F
GT
GT UVA
E&F
UCinc
Raytheon
Raytheon
UVA
UCinc EIT
EIT ADL
ADL
 Files provide a way for a VHDL design to

communicate with the host environment
 File declarations make a file available for use to a
design
 Files can be opened for reading and writing
 In VHDL87, files are opened and closed when their
associated objects come into and out of scope
 In VHDL93 explicit FILE_OPEN() and FILE_CLOSE()
procedures were added
 The package STANDARD defines basic file I/O
routines for VHDL types
 The package TEXTIO defines more powerful
routines handling I/O of text files
Simulation Cycle Revisited
Sequential vs Concurrent Statements RASSP
RASSP
SCRA
SCRAE&F
GT
GT UVA
E&F
UCinc
Raytheon
Raytheon
UVA
UCinc EIT
EIT ADL
ADL
 VHDL is inherently a concurrent language

 AllVHDL processes execute concurrently
 Concurrent signal assignment statements are actually
one-line processes
 VHDL statements execute sequentially within a
process
 Concurrent processes with sequential execution
within a process offers maximum flexibility
 Supports various levels of abstraction
 Supports modeling of concurrent and sequential events
as observed in real systems

Concurrent Statements RASSP
RASSP
SCRA
SCRAE&F
GT
GT UVA
E&F
UCinc
UVA
UCinc EIT
Raytheon
Raytheon EIT ADL
ADL
 Basic granularity of concurrency is the process

 Processes are executed concurrently
 Concurrent signal assignment statements are one-line
processes
 Mechanism for achieving concurrency :
 Processes communicate with each other via signals
 Signal assignments require delay before new value is assumed
 Simulation time advances when all active processes complete
 Effect is concurrent processing
 I.e. order in which processes are actually executed by
simulator does not affect behavior
 Concurrent VHDL statements include :
 Block, process, assert, signal assignment, procedure call,
component instantiation
Sequential Statements RASSP
RASSP
SCRA
SCRAE&F
GT
GT UVA
E&F
UCinc
UVA
UCinc EIT
Raytheon
Raytheon EIT ADL
ADL
 Statements inside a process execute sequentially
ARCHITECTURE
ARCHITECTURE sequential
sequential OFOF test_mux
test_mux IS
IS
BEGIN
BEGIN
select_proc
select_proc :: PROCESS
PROCESS (x,y)
(x,y)
BEGIN
BEGIN
IF
IF (select_sig
(select_sig == '0')
'0') THEN
THEN
zz <=
<= x;
x;
ELSIF
ELSIF (select_sig
(select_sig == '1')
'1') THEN
THEN
zz <=
<= y;
y;
ELSE
ELSE
zz <=
<= "XXXX";
"XXXX";
END
END IF;
IF;
END
END PROCESS
PROCESS select_proc;
select_proc;
END
END sequential;
sequential;

Packages and Libraries RASSP
RASSP
SCRA
SCRAE&F
GT
GT UVA
E&F
UCinc
UVA
UCinc EIT
Raytheon
Raytheon EIT ADL
ADL
 User defined constructs declared inside

architectures and entities are not visible to other
VHDL components
 Scope of subprograms, user defined data types,
constants, and signals is limited to the VHDL
components in which they are declared
 Packages and libraries provide the ability to

reuse constructs in multiple entities and
architectures
 Items declared in packages can be used (i.e. included)
in other VHDL components

Packages RASSP
RASSP
SCRA
SCRAE&F
GT
GT UVA
E&F
UCinc
UVA
UCinc EIT
Raytheon
Raytheon EIT ADL
ADL
 Packages consist of two parts

 Package declaration -- contains declarations of objects
defined in the package
 Package body -- contains necessary definitions for
certain objects in package declaration
 e.g. subprogram descriptions
 Examples of VHDL items included in packages :

 Basic declarations  Signal declarations
 Types, subtypes  Attribute declarations
 Constants  Component declarations
 Subprograms
 Use clause

Packages
Declaration RASSP
RASSP
SCRA
SCRAE&F
GT
GT UVA
E&F
UCinc
Raytheon
Raytheon
UVA
UCinc EIT
EIT ADL
ADL
 An example of a package declaration :

PACKAGE
PACKAGE my_stuff
my_stuff ISIS
TYPE
TYPE binary
binary IS
IS (( ON,
ON, OFF
OFF );
);
CONSTANT
CONSTANT PI
PI :: REAL
REAL :=
:= 3.14;
3.14;
CONSTANT
CONSTANT My_ID
My_ID :: INTEGER;
INTEGER;
PROCEDURE
PROCEDURE add_bits3(SIGNAL
add_bits3(SIGNAL a, a, b,
b, en
en :: IN
IN BIT;
BIT;
SIGNAL
SIGNAL temp_result,
temp_result, temp_carry
temp_carry :: OUTOUT BIT);
BIT);
END
END my_stuff;
my_stuff;
 Note some items only require declaration while

others need further detail provided in subsequent
package body
 fortype and subtype definitions, declaration is sufficient
 subprograms require declarations and descriptions
Packages
Package Body RASSP
RASSP
SCRA
SCRAE&F
GT
GT UVA
E&F
UCinc
Raytheon
Raytheon
UVA
UCinc EIT
EIT ADL
ADL
 The package body includes the necessary

functional descriptions needed for objects
declared in the package declaration
 e.g. subprogram descriptions, assignments to constants
PACKAGE
PACKAGE BODY
BODY my_stuff
my_stuff ISIS
CONSTANT
CONSTANT My_ID
My_ID :: INTEGER
INTEGER :=
:= 2;
2;
PROCEDURE
PROCEDURE add_bits3(SIGNAL
add_bits3(SIGNAL a, a, b,
b, en
en :: IN
IN BIT;
BIT;
SIGNAL
SIGNAL temp_result,
temp_result, temp_carry
temp_carry :: OUT OUT BIT)
BIT) IS
IS
BEGIN
BEGIN --
-- this
this function
function cancan return
return aa carry
carry
temp_result
temp_result <=
<= (a
(a XOR
XOR b)b) AND
AND en;
en;
temp_carry
temp_carry <=
<= aa AND
AND bb AND
AND en;
en;
END
END add_bits3;
add_bits3;
END
END my_stuff;
my_stuff;

Packages
Use Clause RASSP
RASSP
SCRA
SCRAE&F
GT
GT UVA
E&F
UCinc
Raytheon
Raytheon
UVA
UCinc EIT
EIT ADL
ADL
 Packages must be made visible before their

contents can be used
 The USE clause makes packages visible to entities,
architectures, and other packages
-- use only the binary and add_bits3 declarations

USE my_stuff.binary, my_stuff.add_bits3;
... ENTITY declaration...

... ARCHITECTURE declaration ...
-- use all of the declarations in package my_stuff

USE my_stuff.ALL;
... ENTITY declaration...

... ARCHITECTURE declaration ...
Libraries RASSP
RASSP
SCRA
SCRAE&F
GT
GT UVA
E&F
UCinc
UVA
UCinc EIT
Raytheon
Raytheon EIT ADL
ADL
 Analogous to directories of files

 VHDL libraries contain analyzed (i.e. compiled) VHDL
entities, architectures, and packages
 Facilitate administration of configuration and
revision control
 E.g. libraries of previous designs
 Libraries accessed via an assigned logical name
 Current design unit is compiled into the Work library
 Both Work and STD libraries are always available
 Many other libraries usually supplied by VHDL
simulator vendor
 E.g. proprietary libraries and IEEE standard libraries

Attributes RASSP
RASSP
SCRA
SCRAE&F
GT
GT UVA
E&F
UCinc
UVA
UCinc EIT
Raytheon
Raytheon EIT ADL
ADL
 Attributes provide information about certain

items in VHDL
 E.g. types, subtypes, procedures, functions, signals,
variables, constants, entities, architectures,
configurations, packages, components
 General form of attribute use :
name'attribute_identifier
name'attribute_identifier --
-- read
read as
as “tick”
“tick”
 VHDL has several predefined, e.g :

 X'EVENT -- TRUE when there is an event on signal X
 X'LAST_VALUE -- returns the previous value of signal X
 Y'HIGH -- returns the highest value in the range of Y
 X'STABLE(t) -- TRUE when no event has occurred on
signal X in the past ‘t’ time
Attributes
Register Example RASSP
RASSP
SCRA
SCRAE&F
GT
GT UVA
E&F
UCinc
Raytheon
Raytheon
UVA
UCinc EIT
EIT ADL
ADL
 The following example shows how attributes can

be used to make an 8-bit register
 Specifications :
 Triggerson rising clock edge
 Latches only on enable high
 Has a data setup time of x_setup
 Has propagation delay of prop_delay
ENTITY 8_bit_reg IS
GENERIC (x_setup, prop_delay : TIME);
PORT(enable, clk : IN qsim_state;
a : IN qsim_state_vector(7 DOWNTO 0);
b : OUT qsim_state_vector(7 DOWNTO 0));
END 8_bit_reg;
 qsim_state type is being used - includes logic

values 0, 1, X, and Z
Attributes
Register Example (Cont.) RASSP
RASSP
SCRA
SCRAE&F
GT
GT UVA
E&F
UCinc
Raytheon
Raytheon
UVA
UCinc EIT
EIT ADL
ADL
 The following architecture is a first attempt at the

register
 The use of 'STABLE is to used to detect setup
violations in the data input
ARCHITECTURE first_attempt OF 8_bit_reg IS
BEGIN
PROCESS (clk)
BEGIN
IF (enable = '1') AND a'STABLE(x_setup) AND
(clk = '1') THEN
b <= a AFTER prop_delay;
END IF;
END PROCESS;
END first_attempt;
 What happens if a does not satisfy its setup time

requirement of x_setup?
Attributes
Register Example (Cont.) RASSP
RASSP
SCRA
SCRAE&F
GT
GT UVA
E&F
UCinc
Raytheon
Raytheon
UVA
UCinc EIT
EIT ADL
ADL
 The following architecture is a second and more

robust attempt
 The use of 'LAST_VALUE ensures the clock is
rising from a value of ‘0’
ARCHITECTURE behavior OF 8_bit_reg IS
BEGIN
PROCESS (clk)
BEGIN
IF (enable = '1') AND a'STABLE(x_setup) AND
(clk = '1') AND (clk'LAST_VALUE = '0') THEN
b <= a AFTER delay;
END IF;
END PROCESS;
END behavior;
 An ELSE clause could be added to define the

behavior when the requirements are not satisfied
Operators RASSP
RASSP
SCRA
SCRAE&F
GT
GT UVA
E&F
UCinc
UVA
UCinc EIT
Raytheon
Raytheon EIT ADL
ADL
 Operators can be chained to form complex

expressions, e.g. :
res
res <=
<= aa AND
AND NOT(B)
NOT(B) OR
OR NOT(a)
NOT(a) AND
AND b;
b;
 Can use parentheses for readability and to control the
association of operators and operands
 Defined precedence levels in decreasing order :
 Miscellaneous operators -- **, abs, not
 Multiplication operators -- *, /, mod, rem
 Sign operator -- +, -
 Addition operators -- +, -, &
 Shift operators -- sll, srl, sla, sra, rol, ror
 Relational operators -- =, /=, <, <=, >, >=
 Logical operators -- AND, OR, NAND, NOR, XOR, XNOR
Operators
Examples RASSP
RASSP
SCRA
SCRAE&F
GT
GT UVA
E&F
UCinc
Raytheon
Raytheon
UVA
UCinc EIT
EIT ADL
ADL
 The concatenation operator &

VARIABLE
VARIABLE shifted,
shifted, shiftin
shiftin :: BIT_VECTOR(0
BIT_VECTOR(0 TO
TO 3);
3);
...
...
shifted
shifted :=
:= shiftin(1
shiftin(1 TO
TO 3)
3) && '0';
'0';
0 1 2 3
SHIFTIN 1 0 0 1
SHIFTED 0 0 1 0
 The exponentiation operator **

xx :=
:= 5**5
5**5 --
-- 5^5,
5^5, OKOK
yy :=
:= 0.5**3
0.5**3 --
-- 0.5^3,
0.5^3, OK
OK
xx :=
:= 4**0.5
4**0.5 --
-- 4^0.5,
4^0.5, Illegal
Illegal
yy :=
:= 0.5**(-2)
0.5**(-2) ---- 0.5^(-2),
0.5^(-2), OK
OK
RASSP
SCRA
SCRAE&F
GT
GT UVA
E&F
UCinc
UVA
UCinc EIT
Raytheon
Raytheon EIT ADL
ADL
 Introduction
 Examples
 Summary

Examples RASSP
RASSP
SCRA
SCRAE&F
GT
GT UVA
E&F
UCinc
UVA
UCinc EIT
Raytheon
Raytheon EIT ADL
ADL
 Build a library of logic gates

 AND, OR, NAND, NOR, INV, etc.
 Include sequential elements
 DFF, Register, etc.
 Include tri-state devices
 Use 4-valued logic
 ‘X’,
‘0’, ‘1’, ‘Z’
 Encapsulate global declarations in a package

Global Package RASSP
RASSP
SCRA
SCRAE&F
GT
GT UVA
E&F
UCinc
UVA
UCinc EIT
Raytheon
Raytheon EIT ADL
ADL
PACKAGE resources IS
TYPE level IS ('X', '0', '1', 'Z'); -- enumerated type
TYPE level_vector IS ARRAY (NATURAL RANGE <>) OF level;

-- type for vectors (buses)
SUBTYPE delay IS TIME; -- subtype for gate delays
-- Function and procedure declarations go here
END resources;

Two Input AND Gate Example RASSP
RASSP
SCRA
SCRAE&F
GT
GT UVA
E&F
UCinc
UVA
UCinc EIT
Raytheon
Raytheon EIT ADL
ADL
USE work.resources.all;
ENTITY and2 IS
GENERIC(trise : delay := 10 ns;

tfall : delay := 8 ns); ARCHITECTURE behav OF and2 IS
PORT(a, b : IN level; BEGIN

c : OUT level);
one : PROCESS (a,b)
END and2;
BEGIN
IF (a = '1' AND b = '1') THEN
c <= '1' AFTER trise;
ELSIF (a = '0' OR b = '0') THEN
c <= '0' AFTER tfall;
ELSE
c<= 'X' AFTER (trise+tfall)/2;
END IF;
END PROCESS one;
END behav;
And Gate Simulation Results RASSP
RASSP
SCRA
SCRAE&F
GT
GT UVA
E&F
UCinc
UVA
UCinc EIT
Raytheon
Raytheon EIT ADL
ADL

Tri-State Buffer Example RASSP
RASSP
SCRA
SCRAE&F
GT
GT UVA
E&F
UCinc
UVA
UCinc EIT
Raytheon
Raytheon EIT ADL
ADL
USE work.resources.all;
ENTITY tri_state IS
ARCHITECTURE behav OF tri_state IS
GENERIC(trise : delay := 6 ns;
tfall : delay := 5 ns; BEGIN
thiz : delay := 8 ns);
one : PROCESS (a,e)
PORT(a : IN level;
e : IN level; BEGIN
b : OUT level); IF (e = '1' AND a = '1') THEN
-- enabled and valid data
END tri_state; b <= '1' AFTER trise;
ELSIF (e = '1' AND a = '0') THEN
b <= '0' AFTER tfall;
ELSIF (e = '0') THEN -- disabled
b <= 'Z' AFTER thiz;
ELSE -- invalid data or enable
b <= 'X' AFTER (trise+tfall)/2;
END IF;
END PROCESS one;
END behav;

Tri-State Buffer Simulation
Results RASSP
RASSP
SCRA
SCRAE&F
GT
GT UVA
E&F
UCinc
Raytheon
Raytheon
UVA
UCinc EIT
EIT ADL
ADL

D Flip Flop Example RASSP
RASSP
SCRA
SCRAE&F
GT
GT UVA
E&F
UCinc
UVA
UCinc EIT
Raytheon
Raytheon EIT ADL
ADL
USE work.resources.all; ARCHITECTURE behav OF dff IS

BEGIN
ENTITY dff IS one : PROCESS (clk)
BEGIN
GENERIC(tprop : delay := 8 ns; -- check for rising clock edge
tsu : delay := 2 ns); IF ((clk = '1' AND clk'LAST_VALUE = '0')
AND enable = '1') THEN -- ff enabled
PORT(d : IN level; -- first, check setup time requirement
clk : IN level; IF (d'STABLE(tsu)) THEN
enable : IN level; -- check valid input data
q : OUT level; IF (d = '0') THEN
qn : OUT level); q <= '0' AFTER tprop;
qn <= '1' AFTER tprop;
END dff; ELSIF (d = '1') THEN
q <= '1' AFTER tprop;
qn <= '0' AFTER tprop;
ELSE -- else invalid data
q <= 'X';
qn <= 'X';
END IF;
ELSE -- else violated setup time requirement
q <= 'X';
qn <= 'X';
END IF;
END IF;
END PROCESS one;
END behav;
D Flip Flop Simulation Results RASSP
RASSP
SCRA
SCRAE&F
GT
GT UVA
E&F
UCinc
UVA
UCinc EIT
Raytheon
Raytheon EIT ADL
ADL

RASSP
SCRA
SCRAE&F
GT
GT UVA
E&F
UCinc
UVA
UCinc EIT
Raytheon
Raytheon EIT ADL
ADL
 Introduction
 Examples
 Summary

Summary RASSP
RASSP
SCRA
SCRAE&F
GT
GT UVA
E&F
UCinc
UVA
UCinc EIT
Raytheon
Raytheon EIT ADL
ADL
 VHDL is a worldwide standard for the description

and modeling of digital hardware
 VHDL gives the designer many different ways to
describe hardware
 Familiar programming tools are available for
complex and simple problems
 Sequential and concurrent modes of execution
meet a large variety of design needs
 Packages and libraries support design
management and component reuse

Putting It All Together RASSP
RASSP
SCRA
SCRAE&F
GT
GT UVA
E&F
UCinc
UVA
UCinc EIT
Raytheon
Raytheon EIT ADL
ADL
Package
Generics Entity Ports
Architecture Architecture Architecture
Concurrent Process
Concurrent
Statements
Statements
Sequential Statements
References RASSP
RASSP
SCRA
SCRAE&F
GT
GT UVA
E&F
UCinc
UVA
UCinc EIT
Raytheon
Raytheon EIT ADL
ADL
[Bhasker95] Bhasker, J. A VHDL Primer, Prentice Hall, 1995.

[Calhoun95] Calhoun, J.S., Reese, B.,. “Class Notes for EE-4993/6993: Special Topics in Electrical Engineering
(VHDL)”, Mississippi State University, http://www.erc.msstate.edu/mpl/vhdl-class/html, 1995.
[Coelho89] Coelho, D. R., The VHDL Handbook, Kluwer Academic Publishers, 1989.
[Gajski83] Gajski, Daniel D. and Kuhn, Robert H., "Guest Editors Introduction - New VLSI Tools", IEEE Computer,
pp 11-14, IEEE, 1983
[Hein97] Hein, C., T. Carpenter, A. Gadient, R. Harr, P. Kalutkiewicz, V. Madisetti, “RASSP VHDL Modeling
Terminology and Taxonomy,” Revision 2.2, March 27, 1997.
[Lipsett89] Lipsett, R., C. Schaefer, C. Ussery, VHDL: Hardware Description and Design, Kluwer Academic
Publishers, , 1989.
[LRM94] IEEE Standard VHDL Language Reference Manual, IEEE Std 1076-1993, 1994.
[Navabi93] Navabi, Z., VHDL: Analysis and Modeling of Digital Systems, McGraw-Hill, 1993.
[Menchini94] Menchini, P., “Class Notes for Top Down Design with VHDL”, 1994.
[MG90] An Introduction to Modeling in VHDL, Mentor Graphics Corporation, 1990.
[MG93] Introduction to VHDL, Mentor Graphics Corporation, 1993.
[Perry94] Perry, D. L., VHDL, McGraw-Hill, 1994.
[Smith88] Smith, David, “What is Logic Synthesis”, VLSI Design and Test, October, 1988.
[USE/DA94] USE/DA Standards Survey, 1994.
[VI93] VHDL International Survey, 1993.

References RASSP
RASSP
SCRA
SCRAE&F
GT
GT UVA
E&F
UCinc
UVA
UCinc EIT
Raytheon
Raytheon EIT ADL
ADL
[Walker85] Walker, Robert A. and Thomas, Donald E., "A Model of Design Representation and Syntheses", 22nd
Design Automation Conference, pp. 453-459, IEEE, 1985
[Williams94] Williams, R. D., "Class Notes for EE 435: Computer Organization and Design", University of Virginia,
1994.

VHDL 강좌 m10 - 23

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Basic VHDL

RASSP Education & Facilitation

Copyright  1995-1998 RASSP E&F

RASSP DESIGN LIBRARIES AND DATABASE

 Introduce basic VHDL constructs

 Introduce the VHDL simulation cycle and timing

 Illustrate VHDL’s utility as a digital hardware

Copyright  1995-1998 RASSP E&F

Copyright  1995-1998 RASSP E&F

 Basic VHDL Constructs

Copyright  1995-1998 RASSP E&F

 VHDL Model Components

 Basic VHDL Constructs

Copyright  1995-1998 RASSP E&F

 In a survey of 71 US universities (representing

Copyright  1995-1998 RASSP E&F

 VHDL is an international IEEE standard

 VHDL enables hardware modeling from the gate

 VHDL provides a mechanism for digital design

Copyright  1995-1998 RASSP E&F

 Very High Speed Integrated Circuit (VHSIC)

 Woods Hole Workshop

 In July 1983, a team of Intermetrics, IBM and

Copyright  1995-1998 RASSP E&F

Cell, Module Plans

Independently Describe: 1) Resolution of INTERNAL (kernel) details

High Res. All functions modeled Low Res.

Model resolves information at any of the levels spanned,

Model optionally resolves information at levels spanned

Model resolves partial information at levels spanned, such

Model does not contain information on attribute

Virtual Prototype Internal External

Copyright  1995-1998 RASSP E&F [Hein97]

RASSP Taxonomy (Cont.)

Copyright  1995-1998 RASSP E&F [Hein97]

RASSP Taxonomy (Cont.)

Copyright  1995-1998 RASSP E&F [Hein97]

RASSP Taxonomy (Cont.)

Copyright  1995-1998 RASSP E&F [Hein97]

 Allows for various design methodologies

Generics Entity Ports

Architecture Architecture Architecture

 VHDL Design Example

 Basic VHDL Constructs

Copyright  1995-1998 RASSP E&F

 Problem: Design a single bit half adder with carry

Copyright  1995-1998 RASSP E&F

 As a first step, the entity declaration describes

PORT( x, y, enable: IN BIT;

Copyright  1995-1998 RASSP E&F

 A high level description can be used to describe

 The model can then be simulated to verify

 A second method is to use logic equations to

ARCHITECTURE half_adder_b OF half_adder IS

 Again, the model can be simulated at this level to

Copyright  1995-1998 RASSP E&F

 As a third method, a structural description can

 These gates can be pulled from a library of parts

Copyright  1995-1998 RASSP E&F

ARCHITECTURE half_adder_c OF half_adder IS

FOR ALL : and2 USE ENTITY gate_lib.and2_Nty(and2_a);

-- description is continued on next slide

Copyright  1995-1998 RASSP E&F