Embedded

Computing Systems
 Chapter One
Introduction to embedded
systems

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What is a System?
A system is an arrangement where all its component work according to the
specific defined rules. It is a method of organizing, working, or performing one
or more tasks according to a fixed plan.

What is an Embedded System?

EMBEDDED SYSTEM is a combination of computer software and hardware
which is either fixed in capability or programmable. An embedded system can
be either an independent system, or it can be a part of a large system. It is
mostly designed for a specific function or functions within a larger system. For
example, a fire alarm is a common example of an embedded system which can
sense only smoke.

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Example of Embedded Systems

Laser Printer
Laser Printers are using embedded systems to manage various aspect of the
printing. Apart from performing the main task of printing, it has to take user
inputs, manage communication with the computer system, to handle faults, and
sense papers left on the tray, etc.
Here, the main task of the microprocessor is to understand the text and control
the printing head in such a way that it discharges ink where it is needed.
To perform this, it needs to decode the different files given to it and understand
the font and graphics. It will consume substantial CPU time to process the data
as well as it has to take user inputs, control motors, etc.

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History of Embedded system
Here, are important milestones from the history of embedded system:
• In 1960, embedded system was first used for developing Apollo Guidance
System by Charles Stark Draper at MIT.
• In 1965, Autonetics, developed the D-17B, the computer used in the
Minuteman missile guidance system.
• In 1968, the first embedded system for a vehicle was released.
• Texas Instruments developed the first microcontroller in 1971.
• In 1987, the first embedded OS, VxWorks, was released by Wind River.
• Microsoft's Windows embedded CE in 1996.
• By the late 1990s, the first embedded Linux system appeared.
• The embedded market reach $140 billion in 2013.
• Analysts are projecting an embedded market larger than $40 billion by
2030. 5
Characteristics of an Embedded
System
Following are important characteristics of an
embedded system:
• Requires real time performance
• It should have high availability and reliability.
• Developed around a real-time operating system
• Usually, have easy and a diskless operation,
ROM boot
• Designed for one specific task
• It must be connected with peripherals to
connect input and output devices.
• Offers high reliability and stability
• Needed minimal user interface
• Limited memory, low cost, fewer power
consumptions
• It does not need any secondary memory in
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computer.
Important terminologies used in embedded system
Here, are important terms used in embedded system.

Reliability:
This measure of the survival probability of the system when the function is critical during the run time.
Fault-Tolerance:
Fault-Tolerance is the capability of a computer system to survive in the presence of faults.
Real-Time:
Embedded system must meet various timing and other constraints. They are imposed on it by the real-time natural
behavior of the external world.
For example, an airforce department which keeps track of incoming missile attacks must precisely calculate and plan
their counter-attack due to hard real-time deadline. Otherwise, it'll get destroyed.
Flexibility:
It's building systems with built-in debugging opportunities which allows remote maintenance.
For example, you are building a spacecraft which will land on another planet to collect various types of data and send
collected detail back to us. If this spacecraft went insane and lost the control, we should be able to make some
important diagnostic. So, flexibility is vital while designing an embedded system.
Portability:
Portability is a measure of the ease of using the same embedded software in various environments. It requires
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generalized abstractions between the application program logic itself and the low-level system interfaces.
What is Microcontroller?
A microcontroller is a single-chip VLSI unit which is also called microcomputer. It
contains all the memory and I/O interfaces needed, whereas a general-purpose
microprocessor needs additional chips to offered by these necessary functions.
Microcontrollers are widely used in embedded systems for real-time control
applications.

What is a Microprocessor?
A microprocessor is a single chip semiconductor device. Its CPU contains a
program counter, an ALU a stack pointer, working register, a clock timing circuit.
It also includes ROM and RAM, memory decoder, and many serial and parallel
ports.

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Architecture of the Embedded System
Below is basic architecture of the Embedded System:

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1) Sensor:
Sensor helps you to measures the physical quantity and converts it to an electrical signal. It also
stores the measured quantity to the memory. This signal can be ready by an observer or by any
electronic instrument such as A2D converter.
2) A-D Converter:
A-D converter (analog-to-digital converter) allows you to convert an analog signal sent by the
sensor into a digital signal.
3) Memory:
Memory is used to store information. Embedded System majorly contains two memory cells 1)
Volatile 2) Non-volatile memory.
4) Processor & ASICs (Application-Specific Integrated Circuit):
This component processes the data to measure the output and store it to the memory.
5) D-A Converter:
D-A converter (A digital-to-analog converter) helps you to convert the digital data fed by the
processor to analog data.
6) Actuator:
An actuator allows you to compare the output given by the D-A converter to the actual 10output
Types of Embedded System
Three types of Embedded Systems are:
Small Scale Embedded Systems:
This embedded system can be designed with a single 8 or 16-bit microcontroller. It can be
operated with the help of a battery. For developing small scale embedded system, an
editor, assembler, integrated development environment (IDE), and cross assembler are the
most vital programming tools.
Medium Scale Embedded Systems:
These types of embedded systems are designed using 16 or 32-bit microcontrollers. These
systems offer both hardware and software complexities. C, C++, Java, and source code
engineering tool, etc. are used to develop this kind of embedded system.
Sophisticated Embedded Systems
This type of embedded systems have lots of hardware and software complexities. You may
require IPS (Instruction-Set Processors), ASIPS (Application Specific Instruction-Set
Processors), PLA (Programmable Logic Array), configuration processor, or scalable
processors. For the development of this system, you need hardware and software co-
design & components which needs to combine in the final system. 11
Difference between Microprocessor and Microcontroller
Microprocessor Microcontroller
It uses functional blocks like register, ALU, timing, It uses functional blocks of microprocessors like
and control units. RAM, timer, parallels I/O, ADC, and DAC.
In Microprocessor, bit handling instruction is less, Microcontroller offers many kinds of bit handling
One or two types only. instruction.
Offers rapid movements of code and data between Offers rapid movements of code and data in the
external memory and microprocessor. microcontroller.
Helps you to design general purpose digital Helps you to design application-specific dedicated
computers system. systems.
It allows you to do multitasking at a time. It is a single task oriented system.
In Microprocessor system, you can decide the In Microcontroller system, the fixed number for
number of memory or I/O ports needed. memory or I/O makes a microcontroller ideal to
complete the specific task.
Offers support for external memory and I/O ports, This type of system is lightweight and cheaper
which makes it heavier and costlier system. compares to the microprocessor.

External devices need more space, and their power This type of system consumes less amount of space,
consumption is quite higher. and power consumption is also very low. 12
Application of Embedded Systems
Following are an important application of embedded system:
Robotic science:
• Ground Vehicles
• Drones
• Underwater Vehicles
Medical
• Dialysis Machine
• Infusion Pumps
• Cardiac Monitor
• Prosthetic Device
Networking
• Router
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Home Devices:
• TVs
• Digital Alarm
• Air Conditioner
• DVD Video Player
• Cameras
Automobiles
• Fuel Injection
• Door Locks
• Air Bags
• Parking Assistant System
• Anti-stealing Alarms
Industrial Control
• Robotics
• Nuclear Reactors 14
Advantages of Embedded System
Here, are Pros/benefits of using Embedded System:

• Small size and faster to load

• More specific to one task
• Easy to manage
• Low cost
• Spend less resources
• Its operating system is dedicated to one device so performance is good
and use less resources like memory and micro-processors

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Disadvantages of Embedded System
Here, are important cons/ drawbacks of using embedded system.

• Difficult to upgrade
• If any problem occurs then you need to reset settings
• Nearly not scalable
• Hardware is limited
• Troubleshooting is difficult
• Difficult to transfer data from one system to other

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Product Life Cycle
As we learn software/hardware development tools and techniques, we can
place them into the framework presented in this section. As illustrated in Figure
bellow. The development of a product follows an analysis-design-
implementation-testing-deployment cycle. For complex systems with long life-
spans, we transverse multiple times around the life cycle. For simple systems, a
onetime pass may suffice.

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The following measures are often considered during the analysis phase of a project:

• Safety: The risk to humans or the environment

• Accuracy: The difference between the expected truth and the actual parameter
• Response time: The time between a triggering event and the resulting action
• Bandwidth: The amount of information processed per time
• Maintainability: The flexibility with which the device can be modified
• Testability: The ease with which proper operation of the device can be verified
• Compatibility: The conformance of the device to existing standards
• Mean time between failure: The reliability of the device, the life of a product
• Size and weight: The physical space required by the system
• Power: The amount of energy it takes to operate the system
• Nonrecurring engineering cost (NRE cost): The one-time cost to design and test
• Unit cost: The cost required to manufacture one additional product
• Time-to-prototype: The time required to design, build, and test an example system
• Time-to-market: The time required to deliver the product to the customer
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• Human factors: The degree to which our customers like/appreciate the product
Quality Design
Embedded system development is similar to other engineering tasks. We can choose
to follow welled-fined procedures during the development and evaluation phases, or
we can meander in a haphazard way and produce code that is hard to test and harder
to change. The ultimate goal of the system is to satisfy the stated objectives such as
accuracy, stability, and input/output relationships. Nevertheless it is appropriate to
separately evaluate the individual components of the system. If we need to evaluate
the quality of our software. There are two categories of performance criteria with
which we evaluate the “goodness” of our software. Quantitative criteria include
dynamic efficiency (speed of execution), static efficiency (memory requirements),
and accuracy of the results. Qualitative criteria centre on ease of software
maintenance. Another qualitative way to evaluate software is ease of
understanding. If your software is easy to understand then it will be:

Easy to debug (fix mistakes)

Easy to verify (prove correctness)
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Easy to maintain (add features)
Debugging Theory
Debugging is the process of detecting and removing of existing and potential
errors (also called as ‘bugs’)

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Black-box testing is simply observing the inputs and outputs without looking
inside. Black-box testing has an important place in debugging a module for its
functionality.

White-box testing allows you to control and observe the internal workings of a
system.

A common mistake made by new engineers is to just perform black box testing.
Effective debugging uses both. One must always start with black-box testing by
subjecting a hardware or software module to appropriate test cases. Once we
document the failed test cases, we can use them to aid us in effectively
performing the task of white-box testing.

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Real Time Systems
Real time system means that the system is subjected to real time, i.e., response
should be guaranteed within a specified timing constraint or system should meet
the specified deadline. For example: flight control system, real time monitors etc.
Types of real time systems based on timing constraints:
1. Hard real time system –This type of system can never miss its deadline.
Missing the deadline may have disastrous consequences. The usefulness of result
produced by a hard real time system decreases abruptly and may become
negative if tardiness increases. Tardiness means how late a real time system
completes its task with respect to its deadline. Example: Flight controller system.
2. Soft real time system –This type of system can miss its deadline
occasionally with some acceptably low probability. Missing the deadline have no
disastrous consequences. The usefulness of result produced by a soft real time
system decreases gradually with increase in tardiness. Example: Telephone
switches.
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 Chapter Two
Embedded ARM microcontrollers

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Computers, Processors, and Microcontrollers
A computer combines a central processing unit (CPU), random access memory
(RAM), read only memory (ROM), and input/output (I/O) ports.
Software is an ordered sequence of very specific instructions that are stored in
memory, defining exactly what and when certain tasks are to be performed.

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The CPU or processor executes the software by retrieving (from memory) and
interpreting these instructions one at a time. An ARM Cortex-M microcontroller
includes a processor, memory and input/output. The processor, memory and
peripherals are connected via multiple buses. Because instructions are fetched
via the ICode bus and data are fetched via the System bus, the Cortex M is
classified as a Harvard architecture. Having multiple busses allows the system to
do several things simultaneously. For example, the processor could be reading
an instruction from ROM using the ICode bus and writing data to RAM using
the System bus.

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The ARM Cortex-M processor has four major components, as illustrated in the Figure.
There are bus interface units (BIU) that read data from the bus during a read cycle and write
data onto the bus during a write cycle. The BIU always drives the address bus and the control
signals of the bus.

The effective address register (EAR) contains the memory address used to fetch the data
needed for the current instruction. Cortex-M microcontrollers execute Thumb instructions
extended with Thumb-2 technology.

The control unit (CU) orchestrates the sequence of operations in the processor. The CU issues
commands to the other three components. The instruction register (IR) contains the operation
code (or op code) for the current instruction. When extended with Thumb-2 technology, op
codes are either 16 or 32 bits wide.

The arithmetic logic unit (ALU) performs arithmetic and logic operations. Addition,
subtraction, multiplication and division are examples of arithmetic operations. Examples of
logic operations are, and, or, exclusive-or, and shift. Many processors used in embedded
applications support specialized operations such as table lookup, multiply and accumulate,
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An application-specific integrated circuit (ASIC) is digital logic that solves a very
specific problem.

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A very small microcomputer, called a microcontroller, contains all the
components of a computer (processor, memory, I/O) on a single chip.

In an embedded system the software is converted to machine code, which is a

list of instructions, and stored in non-volatile flash ROM. As instructions are
fetched, they are placed in a pipeline. This allows instruction fetching to run
ahead of execution. Instructions on the Cortex-M processor are fetched in
order and executed in order. However, it can execute one instruction while
fetching the next. Many high-speed processors allow out of order execution,
support parallel execution on multiple cores, and employ branch prediction.

On the ARM Cortex-M processor, an instruction may read memory or write

memory, but does not read and write memory in the same instruction. Each of
the phases may require one or more bus cycles to complete. Each bus cycle
reads or writes one piece of data. Because of the multiple bus architecture,
most instructions execute in one or two cycles. 28
Bellow, a simplified block diagram of a microcontroller based on the ARM Cortex-
M processor. It is a Harvard architecture because it has separate data and
instruction buses.

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The instruction set combines the high performance typical of a 32-bit processor
with high code density typical of 8-bit and 16-bit microcontrollers. Instructions
are fetched from flash ROM using the ICode bus. Data are exchanged with
memory and I/O via the system bus interface. There are many sophisticated
debugging features utilizing the DCode bus.

An interrupt is a hardware-triggered software function, which is extremely

important for real-time embedded systems.

The latency of an interrupt service is the time between hardware trigger and
software response. Some internal peripherals, like the nested vectored interrupt
controller (NVIC), communicate directly with the processor via the private
peripheral bus (PPB). The tight integration of the processor and interrupt
controller provides fast execution of interrupt service routines (ISRs),
dramatically reducing the interrupt latency.
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The Software Model
The process described in this section applies to both assembly and C. Either the ARM Keil™
uVision® or the Texas Instruments Code Composer Studio™ (CCStudio) integrated
development environment (IDE) can be used to develop software for the Cortex M
microcontrollers. Both include an editor, assembler, compiler, and simulator. Furthermore,
both can be used to download and debug software on a real microcontroller. Either way, the
entire development process is contained in one application, as shown:

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ARM Cortex-M Assembly Language
There are many ARM processors, and we will focuses on Cortex-M
microcontrollers, which executes Thumb instructions extended with Thumb-2
technology. This section does not present all the Thumb instructions. Rather, we
present a few basic instructions.
Syntax
Assembly instructions have four fields separated by spaces or tabs as illustrated:

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Labels: The label field is optional and starts in the first column and is used to identify the
position in memory of the current instruction. You must choose a unique name for each
label.
Opcodes or pseudo-ops: The opcode field specifies which processor command to execute.
The twelve op codes we will present in this section are LDR STR MOV PUSH POP B BL BX
ADD SUB CPSID and CPSIE . If there is a label there must be at least one space or one tab
between the label and the opcode. If there is no label then there must be at least one
space or one tab at the beginning of the line. There are also pseudo-ops that the
assembler uses to control features of the assembly process. An op code generates
machine instructions that get executed by the processor at run time, while a pseudo-op
code generates instructions to the assembler that get interpreted at assembly time.
Operands: The operand field specifies where to find the data to execute the instruction.
Thumb instructions have 0, 1, 2, 3, or more operands, separated by commas.
Comments: The comment field is optional and is ignored by the assembler, but allows you
to describe the software, making it easier to understand. You can add optional spaces
between operands in the operand field. However, a semicolon must separate the operand
and comment fields. Good programmers add comments to explain what you are doing,
why you are doing it, how it was tested, and how to change it in the future. Everything 33
after the semicolon is a comment.
Addressing modes and operands
A fundamental issue in software design is the differentiation between data and
addresses. Another name for address is pointer. It is in assembly language
programming in general and addressing modes in specific that this
differentiation becomes clear. When we put the number 1000 into Register R0,
whether this is data or address depends on how the 1000 is used.

The addressing mode is the format of instruction uses to specify the memory
location to read or write data. We will see five addressing modes in this class:

Immediate Data within the instruction MOV R0,#1

Indexed Data pointed to by register LDR R0,[R1]
Indexed with offset Data pointed to by register LDR R0,[R1,#4]
PC-relative Location is offset relative to PC BL Incr 34
No addressing mode: Some instructions operate completely within the processor
and require no memory data fetches. For example, the ADD R1,R2,R3 instruction
performs R2+R3 and stores the sum into R1.
Immediate addressing mode: If the data is found in the instruction itself, like
MOV R0,#1 , the instruction uses immediate addressing mode.
Indexed addressing mode: A register that contains the address or location of data is
called a pointer or index register. Indexed addressing mode uses a register pointer to
access memory. There are many variations of indexed addressing. In this class, you
will use two types of indexed addressing. The form [Rx] uses Register Rx as a
pointer, where Rx is any of the Registers from R0 to R12. The second type you will
need is called indexed with offset, which has the form [Rx,#n] , where n is a number
from -255 to 4095. This addressing mode will access memory at Rx+n, without
modifying Rx.
PC-relative addressing mode: The addressing mode that uses the PC as the pointer is
called PC-relative addressing mode. It is used for branching, for calling functions, and
accessing constant data stored in ROM. The addressing mode is called PC-relative
because the machine code contains the address difference between where35 the
List of twelve instructions
We will only need 12 assembly instructions in order to design our own real-time
operating system. The following lists the load and store instructions we will
need.

LDR Rd, [Rn] ; load 32-bit memory at [Rn] to Rd

STR Rt, [Rn] ; store Rt to 32-bit memory at [Rn]
LDR Rd, [Rn, #n] ; load 32-bit memory at [Rn+n] to Rd
STR Rt, [Rn, #n] ; store Rt to 32-bit memory at [Rn+n]

Let M be the 32-bit value specified by the 12-bit constant #imm12. When Rd is
absent for add and subtract, the result is placed back in Rn . The following lists a
few more instructions we will need.
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MOV Rd, Rn ;Rd = Rn
MOV Rd, #imm12 ;Rd = M
ADD Rd, Rn, Rm ;Rd = Rn + Rm
ADD Rd, Rn, #imm12 ;Rd = Rn + M
SUB Rd, Rn, Rm ;Rd = Rn - Rm
SUB Rd, Rn, #imm12 ;Rd = Rn - M
CPSID I ;disable interrupts, I=1
CPSIE I ;enable interrupts, I=0

Normally the computer executes one instruction after another in a linear fashion. In particular,
the next instruction to execute is typically found immediately following the current instruction.
We use branch instructions to deviate from this straight line path. These branches use PC-
relative addressing.

B label ;branch to label

BX Rm ;branch indirect to location specified by Rm 37
These are the push and pop instructions we will need

PUSH {Rn,Rm} ; push Rn and Rm onto the stack

PUSH {Rn-Rm} ; push all registers from Rn to Rm onto stack
POP {Rn,Rm} ; pop two 32-bit numbers off stack into Rn, Rm
POP {Rn-Rm} ; pop multiple 32-bit off stack to Rn – Rm

When pushing and popping multiple registers, it does not matter the order
specified in the instruction. Rather, the registers are stored in memory such that
the register with the smaller number is stored at the address with a smaller
value. For example, consider the execution of PUSH {R1,R4-R6} . Assume the
registers R1, R4, R5, and R6 initially contain the values 1, 4, 5, and 6 respectively.
Figure bellow shows the value from lowest-numbered R1 is positioned at the
lowest stack address. If four entries are popped with the POP {R0,R2,R7,R9}
instruction, the value from the lowest stack address is loaded into the lowest- 38
Observation: To push 32-bit data on the stack, first the SP is decremented by 4, and
then the data are stored from a register to the RAM location pointed to by SP.
Observation: To pop 32-bit data from the stack, first the data are read from the RAM
location pointed to by the SP into a register, and then the SP is incremented by 4.

39
 Chapter Three
Microcontroller Hardware

40
Microcontroller I/O pins

I/O is an important part of embedded systems in general. One of the important

features of an operating system is to manage I/O. Input and output are the
means of an embedded system to interact with its world. The external devices
attached to the microcontroller provide functionality for the system. These
devices connect to the microcontroller through ports. A pin is a specific wire on
the microcontroller through which we perform input or output. A collection of
pins grouped by common functionality is called a port. An input port is
hardware on the microcontroller that allows information about the external
world to enter into the computer. The microcontroller also has hardware called
an output port to send information out to the external world. The GPIO
(General Purpose Input Output) pins on a microcontroller are programmable to
be digital input, digital output, analog input or complex and protocol (like
UART etc.) specific.
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Microcontrollers use most of their pins for I/O (called GPIO), see Figure bellow.
Only a few pins are not used for I/O. Examples of pins not used for I/O include
power, ground, reset, debugging, and the clock. More specifically, the TM4C123
uses 43 of its 64 pins for I/O.
The TM4C1294 uses 90 of its 128 pins for I/O. Similarly, the MSP432 uses 84 of
its 100 pins for I/O.

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An interface is defined as the collection of the I/O port, external electronics,
physical devices, and the software, which combine to allow the computer to
communicate with the external world. An example of an input interface is a
switch, where the operator toggles the switch, and the software can recognize
the switch position. An example of an output interface is a light-emitting diode
(LED), where the software can turn the light on and off, and the operator can
see whether or not the light is shining. There is a wide range of possible inputs
and outputs, which can exist in either digital or analog form. In general, we can
classify I/O interfaces into four categories:

Parallel/Digital - binary data are available simultaneously on a group of lines

Serial - binary data are available one bit at a time on a single line
Analog - data are encoded as an electrical voltage, current or power
Time - data are encoded as a period, frequency, pulse width or phase shift
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In a system with memory-mapped I/O, as shown in Figure bellow, the I/O ports are
connected to the processor in a manner similar to memory. I/O ports are assigned
addresses, and the software accesses I/O using reads and writes to the specific I/O
addresses. These addresses appear like regular memory addresses, except accessing
them results in manipulation of a functionality of the mapped I/O port, hence the
term memory-mapped I/O. As a result, the software inputs from an input port using
the same instructions as it would if it were reading from memory. Similarly, the
software outputs from an output port using the same instructions as it would if it
were writing to memory.

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Most pins on Cortex M microcontrollers can be used for general purpose I/O
(GPIO) called regular functions or for more complex functions called alternate
functions. For example, port pins PA1 and PA0 on the TM4C123 can be either
regular parallel port pins, or an asynchronous serial port called universal
asynchronous receiver/transmitter (UART).
Some of the alternative functions are:

• UART Universal asynchronous receiver/transmitter

• SSI or SPI Synchronous serial interface or serial peripheral interface
• I2C Inter-integrated circuit
• Timer Periodic interrupts
• PWM Pulse width modulation
• ADC Analog to digital converter, measurement analog signals
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The UART can be used for serial communication between computers. It is
asynchronous and allows for simultaneous communication in both directions.
The SSI (also called SPI) is used to interface medium speed I/O devices. For
example, SSI to interface a graphics display.
I2C is a simple I/O bus that used for interface low speed peripheral devices. For
example, use I2C to interface a light sensor and a temperature sensor.
The timer modules to create periodic interrupts.
PWM outputs could be used to apply variable power to motor interfaces. For
example, use PWM to adjust the volume of the buzzer.
The ADC used to measure the amplitude of analog signals, and it is important in
data acquisition systems. For example, connect the microphone to the ADC.

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Figure bellow draws the I/O port structure for
the TM4C123GH6PM. This microcontroller is
used on the EK-TM4C123GXL LaunchPad. Pins on
the TM4C family can be assigned to as many as
eight different I/O functions. Pins can be
configured for digital I/O, analog input, timer I/O,
or serial I/O. For example PB4 can be a digital
I/O, ADC, SSI, PWM, timer or CAN pin. There are
two buses used for I/O. The digital I/O ports are
connected to both the advanced peripheral bus
and the advanced high-performance bus (runs
faster). Because of the multiple buses, the
microcontroller can perform I/O bus cycles
simultaneous with instruction fetches from flash
ROM. The TM4C123GH6PM has eight UART
ports, four SSI ports, four I2C ports, two 12-bit
ADCs, twelve timers, two PWMs, a CAN port, and
a USB interface. There are 43 I/O lines. There are
twelve ADC inputs; each ADC can convert up to
1M samples per second. 47
The TM4C LaunchPad evaluation board (Figure bellow) is a low-cost development
board available as part number EK-TM4C123GXL. The kit provides an integrated Stellar
is In-Circuit Debug Interface (ICDI), which allows programming and debugging of the
on-board TM4C microcontroller. One USB cable is used by the debugger (ICDI), and
the other USB allows the user to develop USB applications (device). The user can
select board power to come from either the debugger (ICDI) or the USB device
(device) by setting the Power selection switch.

48
Phase-Lock-Loop
Normally, the execution speed of a microcontroller is determined by an external crystal. The
Stellaris EKK-LM3S1968 evaluation board has an 8 MHz crystal. The Texas Instruments Tiva
EKLM4F120XL, EK-TM4C123GXL, and EK-TM4C1294-XL boards have a 16 MHz crystal. Most
microcontrollers have a phase-lock-loop (PLL) that allows the software to adjust the
execution speed of the computer. Typically, the choice of frequency involves the tradeoff
between software execution speed and electrical power. In other words, slowing down the
bus clock will require less power to operate and generate less heat. Speeding up the bus
clock obviously allows for more calculations per second.
The default bus speed of the LM3S1968 and TM4C microcontrollers is that of the internal
oscillator, also meaning that the PLL is not initially active. For example, the default bus speed
for the LM3S1968 kit is 12 MHz ±30%. The default bus speed for the TM4C internal oscillator
is 16 MHz ±1%. The internal oscillator is significantly less precise than the crystal, but it
requires less power and does not need an external crystal. This means for most applications
we will activate the main oscillator and the PLL so we can have a stable bus clock.
There are two ways to activate the PLL. We could call a library function, or we could access
the clock registers directly. In general, using library functions creates a better design because
the solution will be more stable (less bugs) and will be more portable (easier to switch
microcontrollers). 49
SysTick Timer
All of the Cortex-M processors contain a standard timer. This is called the
SysTick timer and is a 24-bit countdown timer with autoreload (Fig. bellow).
Once started, the SysTick timer will countdown from its initial value, once it
reaches zero it will raise an interrupt and a new count value will be loaded from
the reload register. The main purpose of this timer is to generate a periodic
interrupt for a real-time operating system (RTOS) or other event driven
software. If you are not running an RTOS, you can also use it as a simple timer
peripheral.

50
The default clock source for the SysTick timer is the Cortex-M CPU clock. It may
be possible to switch to another clock source but this will vary depending on
the actual microcontroller you are using. While the SysTick timer is common to
all the Cortex-M processors, its registers occupy the same memory locations
within the Cortex-M3/-M4 and -M7. In the Cortex-M0 and Cortex-M0+, the
SysTick registers are located in the system control block and have different
symbolic names to avoid confusion. The SysTick timer interrupt line and all of
the microcontroller peripheral lines are connected to the Nested Vector
Interrupt Controller (NVIC).

51
 Chapter Four
Real-time operating systems

52
What is a Real-Time Operating System (RTOS)?

Real-time operating system (RTOS) is an operating system intended to serve

real time application that process data as it comes in, mostly without buffer
delay. The full form of RTOS is Real time operating system.

In a RTOS, Processing time requirement are calculated in tenths of seconds

increments of time. It is time-bound system that can be defined as fixed time
constraints. In this type of system, processing must be done inside the specified
constraints. Otherwise, the system will fail.

53
Why use an RTOS?
Here are important reasons for using RTOS:
• It offers priority-based scheduling, which allows you to separate analytical
processing from non-critical processing.
• The Real time OS provides API (Application Programming Interfaces)
functions that allow cleaner and smaller application code.
• Abstracting timing dependencies and the task-based design results in fewer
interdependencies between modules.
• RTOS offers modular task-based development, which allows modular task-
based testing.
• The task-based API encourages modular development as a task, will typically
have a clearly defined role. It allows designers/teams to work independently on
their parts of the project.
• An RTOS is event-driven with no time wastage on processing time for the
event which is not occur. 54
Components of RTOS
Here, are important Component of RTOS

55
The Scheduler: This component of RTOS tells that in which order, the tasks can
be executed which is generally based on the priority.
Symmetric Multiprocessing (SMP): It is a number of multiple different tasks
that can be handled by the RTOS so that parallel processing can be done.
Function Library: It is an important element of RTOS that acts as an interface
that helps you to connect kernel and application code. This application allows
you to send the requests to the Kernel using a function library so that the
application can give the desired results.
Memory Management: this element is needed in the system to allocate
memory to every program, which is the most important element of the RTOS.
Fast dispatch latency: It is an interval between the termination of the task that
can be identified by the OS and the actual time taken by the thread, which is in
the ready queue, that has started processing.
User-defined data objects and classes: RTOS system makes use of programming
languages like C or C++, which should be organized according to their operation.
56
Terms used in RTOS
Here, are essential terms used in RTOS:
• Task: A set of related tasks that are jointly able to provide some system
functionality.
• Job: A job is a small piece of work that can be assigned to a processor, and that may
or may not require resources.
• Release time of a job: It's a time of a job at which job becomes ready for execution.
• Execution time of a job: It is time taken by job to finish its execution.
• Deadline of a job: It's time by which a job should finish its execution.
• Processors: They are also known as active resources. They are important for the
execution of a job.
• Maximum deadline: It is the allowable response time of a job is called its relative
deadline.
• Response time of a job: It is a length of time from the release time of a job when
the instant finishes. 57
Features of RTOS

Here are important features of RTOS:

• Occupy very less memory

• Consume fewer resources
• Response times are highly predictable
• Unpredictable environment
• The Kernel saves the state of the interrupted task and then determines which
task it should run next.
• The Kernel restores the state of the task and passes control of the CPU for
that task.

58
Factors for selecting an RTOS
Here, are essential factors that you need to consider for selecting RTOS:
• Performance: Performance is the most important factor required to be considered
while selecting for a RTOS.
• Middleware: if there is no middleware support in Real time operating system, then the
issue of time-taken integration of processes occurs.
• Error-free: RTOS systems are error-free. Therefore, there is no chance of getting an
error while performing the task.
• Embedded system usage: Programs of RTOS are of small size. So we widely use RTOS for
embedded systems.
• Maximum Consumption: we can achieve maximum Consumption with the help of
RTOS.
• Task shifting: Shifting time of the tasks is very less.
• Unique features: A good RTS should be capable, and it has some extra features like
how it operates to execute a command, efficient protection of the memory of the
system, etc. 59
Difference between in GPOS and RTOS
Here are important differences between GPOS and RTOS:
General-Purpose Operating System (GPOS) Real-Time Operating System (RTOS)

It used for desktop PC and laptop. It is only applied to the embedded

application.

Process-based Scheduling. Time-based scheduling used like round-robin

scheduling.

Interrupt latency is not considered as Interrupt lag is minimal, which is measured in

important as in RTOS. a few microseconds.

No priority inversion mechanism is present in The priority inversion mechanism is current.

the system. So it can not modify by the system.

Kernel's operation may or may not be Kernel's operation can be preempted.

preempted.
Priority inversion remain unnoticed No predictability guarantees 60
Applications of Real Time Operating System
Real-time systems are used in:
• Airlines reservation system.
• Air traffic control system.
• Systems that provide immediate updating.
• Used in any system that provides up to date and minute information on stock
prices.
• Defence application systems like RADAR.
• Networked Multimedia Systems
• Command Control Systems
• Internet Telephony
• Anti-lock Brake Systems
• Heart Pacemaker 61
Disadvantages of RTOS
Here, are drawbacks/cons of using RTOS system:
• RTOS system can run minimal tasks together, and it concentrates only on
those applications which contain an error so that it can avoid them.
• RTOS is the system that concentrates on a few tasks. Therefore, it is really
hard for these systems to do multi-tasking.
• Specific drivers are required for the RTOS so that it can offer fast response
time to interrupt signals, which helps to maintain its speed.
• Plenty of resources are used by RTOS, which makes this system expensive.
• The tasks which have a low priority need to wait for a long time as the RTOS
maintains the accuracy of the program, which are under execution.
• Minimum switching of tasks is done in Real time operating systems.
• It uses complex algorithms which is difficult to understand.
• RTOS uses lot of resources, which sometimes not suitable for the system.62
Real-Time Task Scheduling

Real-time tasks get generated in response to some events that may either be
external or internal to the system. For example, a task might get generated due
to an internal event such as a clock interrupt occurring every few milliseconds
to periodically poll the temperature of a chemical plant. Another task might get
generated due to an external event such as the user pressing a switch. When a
task gets generated, it is said to have arrived or got released. Every real-time
system usually consists of a number of real-time tasks. The time bounds on
different tasks may be different. We had already pointed out that the
consequences of a task missing its time bounds may also vary from task to task.
This is often expressed as the criticality of a task.

63
Types of Real-Time Tasks

Based on the way real-time tasks recur over a period of time, it is possible to
classify them into three main categories: periodic, sporadic, and aperiodic
tasks. In the following, we discuss the important characteristics of these three
major categories of real-time tasks.

64
Periodic Task: A periodic task is one that repeats after a certain fixed time
interval. The precise time instants at which periodic tasks recur are usually
demarcated by clock interrupts. For this reason, periodic tasks are sometimes
referred to as clock-driven tasks. The fixed time interval after which a task
repeats is called the period of the task. If Ti is a periodic task, then the time
from 0 till the occurrence of the first instance of Ti (i.e. Ti(1)) is denoted by φi,
and is called the phase of the task. The second instance (i.e. Ti(2)) occurs at φi
+ pi. The third instance (i.e. Ti(3)) occurs at φi + 2 ∗ pi and so on. Formally, a
periodic task Ti can be represented by a 4 tuple (φi, pi, ei, di) where pi is the
period of task, ei is the worst case execution time of the task, and di is the
relative deadline of the task. We shall use this notation extensively in future
discussions.

65
To illustrate the above notation to represent real-time periodic tasks, let us consider
the track correction task typically found in a rocket control software. Assume the
following characteristics of the track correction task. The track correction task starts
2000 milliseconds after the launch of the rocket, and recurs periodically every 50
milliseconds then on. Each instance of the task requires a processing time of 8
milliseconds and its relative deadline is 50 milliseconds. Recall that the phase of a task
is defined by the occurrence time of the first instance of the task. Therefore, the phase
of this task is 2000 milliseconds (φi). This task can formally be represented as (2000
mSec (φi), 50 mSec (pi), 8 mSec(ei), 50 mSec(di)). This task is pictorially shown in Fig.
bellow.

66
When the deadline of a task equals its period (i.e. pi=di), we can omit the
fourth tuple. In this case, we can represent the task as Ti= (2000 mSec, 50
mSec, 8 mSec). This would automatically mean pi=di=50 mSec. Similarly, when
φi = 0, it can be omitted when no confusion arises. So, Ti = (100mSec; 20mSec)
would indicate a task with φi = 0, pi=100mSec, ei=20mSec, and di=100mSec.
Whenever there is any scope for confusion, we shall explicitly write out the
parameters Ti = (pi=50 mSecs, ei = 8 mSecs, di = 40 mSecs), etc.

A vast majority of the tasks present in a typical real-time system are periodic.
The reason for this is that many activities carried out by real-time systems are
periodic in nature, for example monitoring certain conditions, polling
information from sensors at regular intervals to carry out certain action at
regular intervals (such as drive some actuators).

67
Sporadic Task: A sporadic task is one that recurs at random instants. A sporadic
task Ti can be is represented by a three tuple:
Ti = (ei, gi, di)
where ei is the worst case execution time of an instance of the task, gi denotes
the minimum separation between two consecutive instances of the task, di is
the relative deadline. The minimum separation (gi) between two consecutive
instances of the task implies that once an instance of a sporadic task occurs, the
next instance cannot occur before gi time units have elapsed. That is, gi
restricts the rate at which sporadic tasks can arise. As done for periodic tasks,
we shall use the convention that the first instance of a sporadic task Ti is
denoted by Ti(1) and the successive instances by Ti(2), Ti(3), etc.
Many sporadic tasks such as emergency message arrivals are highly critical in
nature. For example, in a robot a task that gets generated to handle an obstacle
that suddenly appears is a sporadic task. In a factory, the task that handles fire
conditions is a sporadic task. The time of occurrence of these tasks cannot be
predicted. The criticality of sporadic tasks varies from highly critical 68 to
Aperiodic Task: An aperiodic task is in many ways similar to a sporadic task. An
aperiodic task can arise at random instants. However, in case of an aperiodic
task, the minimum separation gi between two consecutive instances can be 0.
That is, two or more instances of an aperiodic task might occur at the same
time instant. Also, the deadline for an aperiodic tasks is expressed as either an
average value or is expressed statistically. Aperiodic tasks are generally soft
real-time tasks. Examples of aperiodic tasks include operator requests,
keyboard presses, mouse movements, etc. In fact, all interactive commands
issued by users are handled by aperiodic tasks.

69
A Few Basic Concepts for Task Scheduling

Real-time task scheduling essentially refers to determining the order in which

the various tasks are to be taken up for execution by the operating system.
Every operating system relies on one or more task schedulers to prepare the
schedule of execution of various tasks it needs to run. Each task scheduler is
characterized by the scheduling algorithm it employs. A large number of
algorithms for scheduling real-time tasks have so far been developed.

Before focusing on the different classes of schedulers more closely, let us first
introduce a few important concepts and terminologies which would be used in
our later discussions.

70
Valid Schedule: A valid schedule for a set of tasks is one where at most one task is
assigned to a processor at a time, no task is scheduled before its arrival time, and the
precedence and resource constraints of all tasks are satisfied.
Feasible Schedule: A valid schedule is called a feasible schedule, only if all tasks
meet their respective time constraints in the schedule.
Proficient Scheduler: A task scheduler sch1 is said to be more proficient than
another scheduler sch2, if sch1 can feasibly schedule all task sets that sch2 can
feasibly schedule, but not vice versa. That is, sch1 can feasibly schedule all task sets
that sch2 can, but there exists at least one task set that sch2 cannot feasibly
schedule, whereas sch1 can. If sch1 can feasibly schedule all task sets that sch2 can
feasibly schedule and vice versa, then sch1 and sch2 are called equally proficient
schedulers.
Optimal Scheduler: A real-time task scheduler is called optimal, if it can feasibly
schedule any task set that can be feasibly scheduled by any other scheduler. In other
words, it would not be possible to find a more proficient scheduling algorithm than
an optimal scheduler. If an optimal scheduler cannot schedule some task set, then
no other scheduler should be able to produce a feasible schedule for that task set.71
Scheduling Points: The scheduling points of a scheduler are the points on time
line at which the scheduler makes decisions regarding which task is to be run
next. It is important to note that a task scheduler does not need to run
continuously, it is activated by the operating system only at the scheduling
points to make the scheduling decision as to which task to be run next. In a
clock-driven scheduler, the scheduling points are defined at the time instants
marked by interrupts generated by a periodic timer. The scheduling points in an
event-driven scheduler are determined by occurrence of certain events.
Preemptive Scheduler: A preemptive scheduler is one which when a higher
priority task arrives, suspends any lower priority task that may be executing
and takes up the higher priority task for execution. Thus, in a preemptive
scheduler, it cannot be the case that a higher priority task is ready and waiting
for execution, and the lower priority task is executing. A preempted lower
priority task can resume its execution only when no higher priority task is ready.

72
Utilization: The processor utilization (or simply utilization) of a task is the
average time for which it executes per unit time interval. In notations: for a
periodic task Ti, the utilization ui = ei/pi, where ei is the execution time and pi is
the period of Ti. For a set of periodic tasks {Ti}: the total utilization due to all
tasks U = i=1Σ n ei/pi. It is the objective of any good scheduling algorithm to
feasibly schedule even those task sets that have very high utilization, i.e.
utilization approaching 1. Of course, on a uniprocessor it is not possible to
schedule task sets having utilization more than 1.

73
Classification of Real-Time Task Scheduling Algorithms

Several schemes of classification of real-time task scheduling algorithms exist. A

popular scheme classifies the real-time task scheduling algorithms based on
how the scheduling points are defined. The three main types of schedulers
according to this classification scheme are: clock-driven, event-driven, and
hybrid.

• The clock-driven schedulers are those in which the scheduling points are
determined by the interrupts received from a clock.
• In the event-driven ones, the scheduling points are defined by certain events
which precludes clock interrupts.
• The hybrid ones use both clock interrupts as well as event occurrences to
define their scheduling points.
74
A few important members of each of these three broad classes of scheduling
algorithms are the following:

1. Clock Driven
• Table-driven
• Cyclic

2. Event Driven
• Simple priority-based
• Rate Monotonic Analysis (RMA)
• Earliest Deadline First (EDF)

3. Hybrid 75
Clock-driven schedulers are simple and efficient. Therefore, these are
frequently used in embedded applications. Important examples of event-
driven schedulers are Earliest Deadline First (EDF) and Rate Monotonic Analysis
(RMA). Event-driven schedulers are more sophisticated than clock-driven
schedulers and usually are more proficient and flexible than clock-driven
schedulers. These are more proficient because they can feasibly schedule some
task sets which clock-driven schedulers cannot. These are more flexible
because they can feasibly schedule sporadic and aperiodic tasks in addition to
periodic tasks, whereas clock-driven schedulers can satisfactorily handle only
periodic tasks.

76
Clock-Driven Scheduling

Clock-driven schedulers make their scheduling decisions regarding which task to

run next only at the clock interrupt points. Clock-driven schedulers are those for
which the scheduling points are determined by timer interrupts. Clock- driven
schedulers are also called off-line schedulers because these schedulers fix the
schedule before the system starts to run. That is, the scheduler pre-determines
which task will run when. Therefore, these schedulers incur very little run time
overhead. However, a prominent shortcoming of this class of schedulers is that
they cannot satisfactorily handle aperiodic and sporadic tasks since the exact
time of occurrence of these tasks cannot be predicted. For this reason, this type
of schedulers is also called static scheduler.
In this section, we study the basic features of two important clock-driven
schedulers: table-driven and cyclic schedulers.

77
Table-Driven Scheduling

Table-driven schedulers usually pre-compute which task would run when, and
store this schedule in a table at the time the system is designed or configured.
Rather than automatic computation of the schedule by the scheduler, the
application programmer can be given the freedom to select his own schedule
for the set of tasks in the application and store the schedule in a table (called
schedule table) to be used by the scheduler at run time.
An example of a schedule table is shown in Table below. The table shows that
task T1 would be taken up for execution at time instant 0, T2 would start
execution 3 milliseconds afterwards, and so on.

78
An important question that needs to be addressed at this point is what would
be the size of the schedule table that would be required for some given set of
periodic real-time tasks to be run on a system? An answer to this question can
be given as follows: if a set ST = {Ti} of n tasks is to be scheduled, then the
entries in the table will replicate themselves after (Least Common Multiple)
LCM (p1, p2, … ,pn) time units, where p1, p2, …, pn are the periods of T1, T2, ...,
Tn. For example, if we have the following three tasks: (e1=5 msecs, p1=20
msecs), (e2=20 msecs, p2=100 msecs), (e3=30 msecs, p3=250 msecs); then, the
schedule will repeat after every 500 msecs. So, for any given task set, it is
sufficient to store entries only for LCM (p1, p2, … ,pn) duration in the schedule
table. LCM (p1, p2, …, pn) is called the major cycle of the set of tasks ST.

79
A major cycle of a set of tasks is an interval of time on the time line such that in
each major cycle, the different tasks recur identically.

In the reasoning we presented above for the computation of the size of a

schedule table, one assumption that we implicitly made is that φi = 0. That is, all
tasks are in phase.
However, tasks often do have non-zero phase. It would be interesting to
determine what would be the major cycle when tasks have non-zero phase. The
result of an investigation into this issue has been given as Theorem.

80
Theorem 1

The major cycle of a set of tasks ST = {T1, T2, … , Tn} is LCM ({p1, p2, … , pn})
even when the tasks have arbitrary phasing.
Proof: As per our definition of a major cycle, even when tasks have non-zero
phasing, task instances would repeat the same way in each major cycle. Let us
consider an example in which the occurrences of a task Ti in a major cycle be as
shown in Fig. below.

81
As shown in the example, there are k-1 occurrences of the task Ti during a
major cycle. The first occurrence of Ti starts φ time units from the start of the
major cycle. The major cycle ends x time units after the last (i.e. (k-1)th)
occurrence of the task Ti in the major cycle. Of course, this must be the same in
each major cycle.
Assume that the size of each major cycle is M. Then, from an inspection of the
Figure, for the task to repeat identically in each major cycle:
M = (k-1)pi + φ + x
Now, for the task Ti to have identical occurrence times in each major cycle, φ +
x must equal to pi.
Substituting this in above equation, we get, M = (k-1)∗ pi + pi = k∗ pi
So, the major cycle M contains an integral multiple of pi. This argument holds
for each task in the task set irrespective of its phase. Therefore M = LCM ({p1,
p2, … , pn}).
82
Cyclic Schedulers
Cyclic schedulers are very popular and are being extensively used in the
industry. A large majority of all small embedded applications being
manufactured presently are based on cyclic schedulers. Cyclic schedulers are
simple, efficient, and are easy to program. An example application where a
cyclic scheduler is normally used is a temperature controller. A temperature
controller periodically samples the temperature of a room and maintains it at a
preset value. Such temperature controllers are embedded in typical computer-
controlled air conditioners.
Cyclic scheduler repeats a pre-computed schedule. The pre-computed schedule
needs to be stored only for one major cycle. Each task in the task set to be
scheduled repeats identically in every major cycle. The major cycle is divided
into one or more minor cycles (see Fig. below).

83
Each minor cycle is also sometimes called a frame. In the example shown in Fig.
below, the major cycle has been divided into four minor cycles (frames). The
scheduling points of a cyclic scheduler occur at frame boundaries. This means
that a task can start executing only at the beginning of a frame.
The frame boundaries are defined through the interrupts generated by a
periodic timer. Each task is assigned to run in one or more frames. The
assignment of tasks to frames is stored in a schedule table. An example
schedule table is shown.

The size of the frame to be used by the scheduler is an important design

parameter and needs to be chosen very carefully. A selected frame size should
satisfy the following three constraints. 84
Minimum Context Switching:

This constraint is imposed to minimize the number of context switches

occurring during task execution. The simplest interpretation of this constraint is
that a task instance must complete running within its assigned frame. Unless a
task completes within its allocated frame, the task might have to be suspended
and restarted in a later frame. This would require a context switch involving
some processing overhead. To avoid unnecessary context switches, the
selected frame size should be larger than the execution time of each task, so
that when a task starts at a frame boundary it should be able to complete
within the same frame. Formally, we can state this constraint as: max({ei}) < F
where ei is the execution times of the of task Ti, and F is the frame size. Note
that this constraint imposes a lower-bound on frame size, i.e., frame size F must
not be smaller than max({ei}).

85
Minimization of Table Size:
This constraint requires that the number of entries in the schedule table should
be minimum, in order to minimize the storage requirement of the schedule
table. Remember that cyclic schedulers are used in small embedded
applications with a very small storage capacity. So, this constraint is important
to the commercial success of a product. The number of entries to be stored in
the schedule table can be minimized when the minor cycle squarely divides the
major cycle. When the minor cycle squarely divides the major cycle, the major
cycle contains an integral number of minor cycles (no fractional minor cycles).
Unless the minor cycle squarely divides the major cycle, storing the schedule
for one major cycle would not be sufficient, as the schedules in the major cycle
would not repeat and this would make the size of the schedule table large. We
can formulate this constraint as: ⎣M/F⎦ = M/F.
In other words, if the floor of M/F equals M/F, then the major cycle would
contain an integral number of frames.
86
Satisfaction of Task Deadline: This third constraint on frame size is necessary to meet the
task deadlines. This constraint imposes that between the arrival of a task and its deadline,
there must exist at least one full frame. This constraint is necessary since a task should
not miss its deadline, because by the time it could be taken up for scheduling, the
deadline was imminent. Consider this: a task can only be taken up for scheduling at the
start of a frame. If between the arrival and completion of a task, not even one frame
exists, a situation as shown in Fig. below might arise.

In this case, the task arrives sometimes after the kth frame has started. Obviously it
cannot be taken up for scheduling in the kth frame and can only be taken up in the k+1th
frame. But, then it may be too late to meet its deadline since the execution time of a task
can be up to the size of a full frame. This might result in the task missing its deadline since
the task might complete only at the end of (k+1)th frame much after the deadline 87d has
We therefore need a full frame to exist between the arrival of a task and its deadline as
shown in Fig. below, so that task deadlines could be met.

More formally, this constraint can be formulated as follows: Suppose a task arises after
Δt time units have passed since the last frame (see Fig. above). Then, assuming that a
single frame is sufficient to complete the task, the task can complete before its
deadline:
iff (2F − Δt) ≤ di, or 2F ≤ (di + Δt).
Remember that the value of Δt might vary from one instance of the task to another.
The worst case scenario (where the task is likely to miss its deadline) occurs for the task
instance having the minimum value of Δt, such that Δt > 0. This is the worst case
scenario, since under this the task would have to wait the longest before its execution
88
It should be clear that if a task arrives just after a frame has started, then the
task would have to wait for the full duration of the current frame before it can
be taken up for execution. If a task at all misses its deadline, then certainly it
would be under such situations. In other words, the worst case scenario for a
task to meet its deadline occurs for its instance that has the minimum
separation from the start of a frame. The determination of the minimum
separation value (i.e. min(Δt)) for a task among all instances of the task would
help in determining a feasible frame size. We show by Theorem below that
min(Δt) is equal to gcd(F, pi). Consequently, this constraint can be written as:
for every Ti, 2F – gcd(F, pi) ≤ di
Note that this constraint defines an upper-bound on frame size for a task Ti, i.e.,
if the frame size is any larger than the defined upper-bound, then tasks might
miss their deadlines. Expr. above defined the frame size, from the consideration
of one task only. Now considering all tasks, the frame size must be:
smaller than max(gcd(F, pi)+di)/2.
89
Theorem
The minimum separation of the task arrival from the corresponding frame start time
(min(Δt)), considering all instances of a task Ti, is equal to gcd(F, pi).
Proof: Let g = gcd(F, pi), where gcd is the function determining the greatest common divisor of
its arguments. It follows from the definition of gcd that g must squarely divide each of F and
pi. Let Ti be a task with zero phasing. Now, assume that this Theorem is violated for certain
integers m and n, such that the Ti(n) occurs in the mth frame and the difference between the
start time of the mth frame and the nth task arrival time is less than g. That is, 0 < (m ∗ F – n
∗ pi) < g.
Dividing this expression throughout by g, we get:
0 < (m ∗ F/g – n ∗ pi/g) < 1
However, F/g and pi/g are both integers because g is gcd(F, pi,). Therefore, we can write F/g =
I1 and pi/g = I2 for some integral values I1 and I2. Substituting this in Expr. above, we get:
0 < m∗I1 – n∗I2 < 1
Since m∗I1 and n∗I2 are both integers, their difference cannot be a fractional value lying
between 0 and 1. Therefore, this expression can never be satisfied.
It can therefore be concluded that the minimum time between a frame boundary and 90 the
For a given task set it is possible that more than one frame size satisfies all the
three constraints. In such cases, it is better to choose the shortest frame size.
This is because of the fact that the schedulability of a task set increases as
more frames become available over a major cycle.

It should however be remembered that the mere fact that a suitable frame size
can be determined does not mean that a feasible schedule would be found. It
may so happen that there is not enough number of frames available in a major
cycle to be assigned to all the task instances.

We now illustrate how an appropriate frame size can be selected for cyclic
schedulers through a few examples.

91
Examples
Example 1: A cyclic scheduler is to be used to run the following set of periodic
tasks on a uniprocessor: T1 = (e1=1, p1=4), T2 = (e2=1, p2=5), T3 = (e3=1,
p3=20), T4 = (e4=2, p4=20). Select an appropriate frame size.

Solution: For the given task set, an appropriate frame size is the one that
satisfies all the three required constraints. In the following, we determine a
suitable frame size F which satisfies all the three required constraints.
Constraint 1: Let F be an appropriate frame size, then max {ei, F}. From this
constraint, we get F ≥ 2.
Constraint 2: The major cycle M for the given task set is given by M =
LCM(4,5,20) = 20. M should be an integral multiple of the frame size F, i.e., M
mod F = 0. This consideration implies that F can take on the values 2, 4, 5, 10,
20. Frame size of 1 has been ruled out since it would violate the constraint 1.
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Constraint 3: To satisfy this constraint, we need to check whether a selected frame size F satisfies the
inequality: 2F − gcd(F, pi) < di for each pi.
Let us first try frame size 2.
For F = 2 and task T1:
2 ∗ 2 − gcd(2, 4) ≤ 4 ≡ 4 − 2 ≤ 4
Therefore, for p1 the inequality is satisfied.
Let us try for F = 2 and task T2:
2 ∗ 2 − gcd(2, 5) ≤ 5 ≡ 4 − 1 ≤ 5
Therefore, for p2 the inequality is satisfied.
Let us try for F = 2 and task T3:
2 ∗ 2 − gcd(2, 20) ≤ 20 ≡ 4 − 2 ≤ 20
Therefore, for p3 the inequality is satisfied.
For F = 2 and task T4:
2 ∗ 2 − gcd(2, 20) ≤ 20 ≡ 4 − 2 ≤ 20
For p4 the inequality is satisfied.

Thus, constraint 3 is satisfied by all tasks for frame size 2. So, frame size 2 satisfies all the93three
Let us try frame size 4.
For F = 4 and task T1:
2 ∗ 4 − gcd(4, 4) ≤ 4 ≡ 8 − 4 ≤ 4
Therefore, for p1 the inequality is satisfied.
Let us try for F = 4 and task T2:
2 ∗ 4 − gcd(4, 5) ≤ 5 ≡ 8 − 1 ≤ 5
For p2 the inequality is not satisfied. Therefore, we need not look any further.
Clearly, F = 4 is not a suitable frame size.
Let us now try frame size 5, to check if that is also feasible.
For F = 5 and task T1, we have
2 ∗ 5 − gcd(5, 4) ≤ 4 ≡ 10 − 1 ≤ 4
The inequality is not satisfied for T1. We need not look any further. Clearly, F = 5
is not a suitable frame size.
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Let us now try frame size 10.
For F = 10 and task T1, we have
2 ∗ 10 − gcd(10, 4) ≤ 4 ≡ 20 − 2 ≤ 4
The inequality is not satisfied for T1. We need not look any further. Clearly, F=10 is not a
suitable frame size.

Let us try if 20 is a feasible frame size.

For F = 20 and task T1, we have
2 ∗ 20 − gcd(20, 4) ≤ 4 ≡ 40 − 4 ≤ 4
Therefore, F = 20 is also not suitable.
So, only the frame size 2 is suitable for scheduling.

Even though for Example 1 we could successfully find a suitable frame size that satisfies all
the three constraints, it is quite probable that a suitable frame size may not exist for many
problems. In such cases, to find a feasible frame size we might have to split the task (or a few
tasks) that is (are) causing violation of the constraints into smaller sub-tasks that can 95 be
Example 2: Consider the following set of periodic real-time tasks to be
scheduled by a cyclic scheduler: T1 = (e1=1, p1=4), T2 = (e2=2, p2=5), T3 =
(e3=5, p3=20). Determine a suitable frame size for the task set.

Solution:
Using the first constraint, we have F ≥ 5.
Using the second constraint, we have the major cycle M = LCM(4, 5, 20) = 20.
So, the permissible values of F are 5, 10 and 20.
Checking for a frame size that satisfies the third constraint, we can find that no
value of F is suitable.
To overcome this problem, we need to split the task that is making the task-set
not schedulable. It is easy to observe that the task T3 has the largest execution
time, and consequently due to constraint 1, makes the feasible frame sizes
quite large.
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We try splitting T3 into two or three tasks. After splitting T3 into three tasks, we
have:

T3.1 = (20, 1, 20), T3.2 = (20, 2, 20), T3.3 = (20, 2, 20).

The possible values of F now are 2 and 4. We can check that now after splitting
the tasks, F=2 and F=4 become feasible frame sizes.

It is very difficult to come up with a clear set of guidelines to identify the exact
task that is to be split, and the parts into which it needs to be split. Therefore,
this needs to be done by trial and error. Further, as the number of tasks to be
scheduled increases, this method of trial and error becomes impractical since
each task needs to be checked separately. However, when the task set consists
of only a few tasks we can easily apply this technique to find a feasible frame
size for a set of tasks otherwise not schedulable by a cyclic scheduler. 97