LAB VII.

LOW FREQUENCY CHARACTERISTICS OF JUNCTION FIELD EFFECT TRANSISTORS

1. OBJECTIVE
In this lab, you will study the I-V characteristics and a small signal model of Junction Field Effect Transistors (JFET).

2. OVERVIEW
In this lab, we will study the I-V characteristics of JFET and we will investigate the definition of some equivalent circuit parameters in order to make a small signal model of our JFET. You will compare the experimental results with the theoretical results of the equations found in the lab manual.

Information essential to your understanding of this lab: 1. Theoretical background of the JFET (Streetman 6.2) Materials necessary for this Experiment: 1. Standard testing station 2. One JFET (Part: 2N5485) 3. 1 k resistor

3. BACKROUND INFORMATION
3.1 CHART OF SYMBOLS
Here is a chart of symbols used in this lab manual. This list is not all inclusive; however, it does contain the most common symbols and their units.

Symbol IDS ids iDS IDSS VP VDS vds vDS VGS vgs vGS gm rd

Table 1. Chart of the symbols used in this lab. Symbol Name DC drain to source current AC drain to source current = IDS + ids = Total drain to source current Drain saturation current @ VG = 0 Pinch off Voltage DC drain to source Voltage AC drain to source Voltage = VDS + vds = Total drain to source voltage DC gate to source Voltage AC gate to source Voltage = VGS + vgs = Total gate to source voltage Transconductance Drain resistance

Units mA mA mA mA V V V V V V V A/V

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3.2 CHART OF EQUATIONS

All of the equations from the background portion of the manual are shown in the table below.

Table 2. Chart of the equations used in this lab.

Equation Name Formula 1 Saturation Drain to Source V current in a N-type JFET I DSAT = I DSS 1 + GS Vp 2 Transconductance at the I operating point g m = DS 3 Equation for Transconductance at the operating point using known variables Total Drain to Source current, iDS(t)

for 0.5 > VGS -|VP|

I = DS V V GS VDS =const. GS VDS =const.

2I g m = DSS Vp

VGS 1 + VP

for 0.5 > VGS -|VP|

2

I i DSAT (t ) = I DS (0) + DSS 2 V 2 I DSS 1 + GS Vp

VGS Vp

v gs I cos( wt ) + DSS Vp 2

v gs Vp

cos(2wt )

Shift in DC operating point due to AC gate Voltage

I I DS = DSS 2

v gs Vp

3.3 THE I-V CHARACTERISTICS OF A JFET Junction Field Effect Transistors (JFETs) are essentially voltage controlled resistors. Unlike diodes, which have two terminals that we call the cathode and anode; JFETs have three terminals that we call the source, drain and gate. The resistance between the drain and source terminals (RDS) is controlled by the voltage applied between the gate and source terminals (VGS). Since we rarely care about the actual resistance in these devices, but rather about the current flowing through them, we note that the transistor action in a JFET is determined by the flow of majority carriers between the source and the drain (IDS) as a function of VGS. IDS is controlled by VGS because VGS reverse biases the gate to source pn junction. This reduces the cross sectional area of a channel through which the charge carriers (IDS) must flow in order to go from source to drain. (See Streetman and Banerjee section 6.2.) The gate voltage modulates the depletion width of the gate-source pn junction. When the depletion width is made larger (larger VGS reverse bias) the channel cross sectional area is made smaller and the resistance is made larger. For VDS held constant, this means that IDS becomes smaller. Likewise, when VGS is smaller, the channel and IDS become larger. The change in the cross-sectional area of the channel under the gate modulates the current flow. The most important operating region of the JFET occurs at VDS levels beyond the point where the channel cross sectional area becomes zero. The points at which this closing of the channel first occurs are shown in Fig. 1 for several values of VGS by the solid red 64

curve. The places where the data curves intersect the red curve are called the saturation voltages and denoted as VDSAT. The one place where the red curve in Fig. 1 intersects the VGS = 0V blue curve is called the pinch-off voltage and is denoted as VP. When VDS > VDSAT, the JFET is above pinchoff or above saturation and the channel is closed off. As a result, the IDS-VDS curves become reasonably flat. That is to say: RDS = dVDS / dIDS becomes large. The depletion width extends all the way across the channel, pinching it off at the drain side so that the channel cross sectional area becomes zero. This closing of the channel does not cause the resistance of the channel to go to infinity, just the differential resistance to go to infinity. That is to say: VDS/IDS , but dVDS / dIDS . The current flow is now limited by the current flow in the non-pinched off region of the channel. The carriers which reach the pinched off region are rapidly pushed through by the reverse bias of the gate and collected at the drain. Analysis of the device geometry shows that in the pinched off region the current flow is primarily determined by the value of VGS and is relatively independent of VDS. This is the practical region for operating the JFET as an amplifier. The DC and low frequency behavior of a JFET can be specified by its output characteristics: IDS vs. VDS with VGS as a parameter. This is shown in Fig. 1 and is called the common source characteristic. The transfer characteristic, IDSAT vs. VGS (for VDS > VDSAT) is shown in Fig. 2. Detailed information about the characteristics of the device is almost always supplied by the device manufacturer so that engineers can design circuits using them. The data sheets for our 2N5485 n-channel JFET used in this lab can be found online. In rare circumstances, the circuit designer must measure device characteristics or use more limited information supplied by the manufacturer such as IDSS and VP.

12 10 8

VP=3.2V VDSAT=VP+VGS

6 4 2 0

VGS=0.5V 0.25V 0V -0.25V -0.5V -0.75V -1V -1.25V -1.5V -1.75V -2V -2.25V -2.5V -2.75V -3V -3.25V -3.5V 8 10

IDS (mA)

VDS (V)
Fig. 1. 2N5485 JFET IDS VDS characteristics. 65

12 IDS for VDS=10V 10 8 IDS=8.06mA*(1+(VGS/3.2))2

IDSAT (mA)

6 4 2 0 -4 -3 -2 -1 0 1

VGS (V)
Fig. 2. Transfer characteristic (IDS vs. VGS taken @VDS=10V) for a 2N2485 JFET. The solid red
line is a fit using Eqn. (1). The slope of this curve gives the transconductance, gm.

When used as a small signal amplifier the JFET will be operating in the saturation regime or pinched-off mode where VDS > VDSAT. In this regime, the JFET DC IDSAT-VDS characteristic can be approximately described using the following equation IDSAT = IDSS (1 + (VGS / VP))2 for 0.5 > VGS -|VP| (1) Note that VGS is generally negative for n-channel JFETs. We can allow VGS to go slightly positive without destroying the JFET operation since that slightly positive gate voltage will only thin the depletion region without allowing significant current (IGS) to flow through the gate. Knowing information such as IDSS and VP can allow one to responsibly use the JFET in a circuit. The values of IDSS and VP for a given type of transistor vary over ranges, therefore the device manufacturer supplies information on the average and extreme values of these parameters. Moreover the device may not closely obey the relationship given by Eq. (1) since it is overly simplistic, but these kinds of parameters are used anyway. In this experiment the DC characteristics of the transistor will be measured in order to obtain sufficient information to use the device in an amplifier circuit and also to determine how closely Eq. (1) represents the actual device behavior. We will not be building the amplifier circuit in this lab, but you may do so if you wish. Simply look up a simple amplifier circuit and try to build it!

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3.4 SMALL SIGNAL MODELS The simplest possible small signal equivalent circuit of a JFET is shown in Fig. 3. This model is only valid for low frequencies where the capacitance of the gate pn junction is small enough to be ignored. The output circuit (between the source and drain) consists of two elements which we will want to measure in this lab. The first element is a current source with the amplitude of the current given as gm*vgs. vgs is the ac voltage applied to the gate with respect to the source. Usually we would apply a small signal ac voltage on the DC offset voltage of VGS. So the AC voltage would be vgs*cos(wt) and the total gate voltage would be VGS + vgs*cos(wt). gm is called the transconductance and is defined as being equal to the slope of the transfer curve in Fig. 2, which is given by: gm = ABS( dIDS / dVGS ) | with VDS = Held Constant. We calculate this in the lab as: gm = ABS( IDS / VGS ) | with VDS = Held Constant. Combining Eqn. (1) with Eqn. (2) and rearranging slightly allows one to find: gm = (2 IDSS / VP) * (1 + (VGS/VP)) for 0.5 > VGS -|VP| (3) (2b) (2a)

Fig. 3. A small signal equivalent circuit model of a JFET for low frequencies. Equation (3) is evaluated at a fixed value of VDS by varying VGS. The input terminals from the gate to the source appear as a reverse biased diode and are an effective open circuit. The numerical value of gm can be estimated from either Eqn. (3) or from Figs. 1 and 2. The latter approach will be used in this experiment. To find gm from the characteristic curves of Fig. 1, find the desired operating VDS. Then, draw a vertical line through the VDS operating point. On this line find the voltage difference (VGS) between the two nearest IDS-VDS characteristic curves. Extrapolate the two intersection points to the IDS-axis and find IDS. Then use Eq. (2) to find gm. To find gm from the transfer curve of Fig. 2, simply find the slope of the curve at any point! The drain resistance, rd, shunting the gm*vgs current source is included in the model to account for changes in the drain current due to changes in VDS. The value of rd is inversely proportional to the change in IDS with change in VDS. Therefore it is defined as: rd = ( dVDS / dIDS ) | with VGS = Held Constant. We calculate this in the lab as: rd = ( VDS / IDS ) | with VGS = Held Constant. (5) The value of rd can be obtained from the slope of the IDS-VDS curve at any VDS in Fig. 1. One must stay on a single VGS curve, so we write that rd is found at constant VGS. One can use a graphical analysis to obtain rd, or one can simply take the derivative of the data stored using your LabVIEW program. 67 (4)

4. PREPARATION
1. Study Figures 6-4 and 6-5 in Streetman and describe the I-V characteristics of a JFET. Manually re-plot Figure 6-4 (do not scan it or copy it) and describe in your own words the variation of depletion regions and channel as voltage changes. Describe what pinch-off is. Identify the VP in the plot. Manually re-plot Figure 6-5 (b) and identify IDSS. In this plot, describe how to calculate gm in your own words.

5. PROCEDURE
Take special note of the absolute maximum ratings (operating range) of the JFET. These can be found on the first page of the data sheets appended to the end of this manual. Construct the circuit shown in Figure 4.

Figure 4. Circuit diagram for the IDS vs. VDS characteristics measurement of the 2N5485

JFET. Once the circuit has been built, open and execute the program FETIVcurve.vi using LabView to obtain a plot of the IDS vs. VDS characteristic similar to the one shown in Figure 1. This program allows you to set a start voltage for VDS and VGS. It also allows you to set a step size for each of them. FETIVcurve.vi will start at the initial VDS and VGS voltages and then will step the VDS value from its initial value to its final value. After the computer reaches the final value of VDS at a fixed VGS then it will increment VGS. This process will continue until the final values of both VDS and VGS are reached. In the program: FETIVcurve.vi 1] Set all compliance values to 0.010 Amps (10 mA). This is the limit of your JFET. 2] Set VDS to vary from 0.0 V to 20 V in 0.25 V steps. 3] Set VGS to vary from 0.5 V to -3.5 V in -0.25 V incremental steps. (16 steps.) Do not go above 0.5V since you could burn up the transistor. If your transistor burns up, you will have to get another JFET and start over. Save the JFET IDS-VDS data for your report. Note that in 2011, the program stored the data with the title Vce for VDS and Ic for IDS.

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Examine the graph that you now have displayed in the LabVIEW window. Now compare to Fig. 1. Take note of the pinch off locus (dotted red line) on the left part of the graph. The locus passes through the point where the current flattens out at every value of VGS. You can visualize the pinch off locus for your graph, but doing so is extraordinarily unreliable. Instead, you can use the fact that when VGS becomes equal to VP, the current flowing through the transistor will become ~0 for all VDS. In 2011, we do not have a good program for measuring the transfer characteristic (like Fig. 2) so we will estimate the pinch-off voltage VP by using FETIVCurve.vi instead. 1] Find the value of VGS at which the current IDS becomes less than 10-8 A for all VDS. You can do this in LabVIEW with your current set of data by changing the IDS axis (the y-axis) to a logarithmic scale and making sure the lowest value plotted is 10-10 A. 2] Obtain a set of curves using FETIVCurve.vi having VGS steps of 0.1 V that go from an IDS value above 10-5 A to below 10-8 A. Use these curves to estimate the value of VP to within 0.1 V. Note: VP = ABS(VGS) for the first curve which has IDS < 10-8 A for all VDS. When you have done it correctly, your plot should look something like Fig. 5.

1x10-3 1x10
-4

1x10-5

VGS = -2.3 V -2.4 V -2.5 V -2.6 V -2.7 V -2.8 V

IDS (A)

1x10-6 1x10-7 1x10-8 1x10-9 1x10-10 0 4 8 12 VDS (V) 16

-2.9 V

-3.0 V

20

Fig. 5. A graph showing how one can find the pinch-off voltage, VP, of a JFET in lab. Note that the curve having VGS = -3.0V has a current too small for the SMU to measure well. The curve at VGS = -2.9 V is above 10-8 A for most VDS. Consequently, VP ~ 3.0 V. 3] Save your data for plotting in your report. 4] Use your value of VP to fill the values of VDSAT(Exp), IDSAT(Exp) and IDSAT(Eqn 1) in the table below. NOTE: VP = the value of VDS at which saturation occurs when VGS = 0 V. VDSAT = VP + VGS. Use this fact to find the value of IDSAT for each VGS. IDSS = IDS(VGS=0, VDS=VP). You will need to retake your curves or use your saved data. 69

Table 3. Experimental values of Vp, IDSAT, gm, rd and theoretical values of IDSAT.
VGS 0.0 V -0.5 V -1.0 V -1.5 V -2.0 V -2.5 V VDSAT(Exp) VP= IDSAT (Exp) IDSS= IDSAT (Eqn. 1) IDSS= gm rd

Now, plot the IDSAT vs. VGS curve using the experimental values in the table above. This plot should look similar to the Figure 2 and it shows JFET amplifiers transfer (VGS - IDS) characteristic. Suppose you use 2N5485 in an amplifier and assume that your operating point is at VDS = 10 V. Find the transconductance, gm, and drain resistance, rd for each VGS. Enter those values in the table above. We also have LabVIEW programs which can measure the transconductance and drain resistance. 1] Use the program FETrds.vi to measure the JFET drain resistance as a function of VDS for VGS = -1.0 V. Plot your data for VDS varying from 0 to 20 V in 250 mV steps. In addition, add the data point you calculated in the table above. Do your two results agree? 2] Use the program FETgm.vi to measure the JFET transconductance as a function of VGS for VDS = 10.0 V. Plot your data for VGS varying from -4.0 to 0.5 V in 100 mV steps. In addition, add all of the data points you calculated in the table above. Do your two results agree?

6. ANALYSIS
Type a lab report with a cover sheet containing your name, class (including section number), date the lab was performed, and the date the report is due. Use the following outline to draft your lab report. Introduction: Type a summary of the experiment. JFET output characteristics (IDS VDS) o Plot the IDS vs. VDS characteristic. Show your pinch-off locus in the plot. Make sure both axes are labeled and the graph is appropriately titled. Plot the characterisitic twice: Once using Linear IDS and VDS Axes. The second time using a LOG-IDS axis (semi-log plot). MAKE SURE that you label each curve with the value of VGS! o Plot the IDS vs. VDS characteristic which allowed you to find your pinch-off voltage VP. Show how you chose your value for VP. (Semi-log plot again.) o Put in Table 3 with the experimental and theoretical data in it. JFET transfer characteristics (IDS VGS) 70

o Plot the IDSAT vs. VGS curve using your values in Table 3. Plot both experimental and theoretical IDSAT in the same plot. Make sure both axes are labeled and the graph is appropriately titled. o Plot the IDS vs. VDS characteristic again and show how you use this plot to find gm and rd at a VDS equal to 10 V and the specified gate voltages in Table 3. o Plot your rd vs VDS curve for VGS = -1 V Why does rd increase for VDS > VP + VGS ? Make sure you include your hand calculated data point from the table. Does it agree with the measurements obtained using FETrds.vi? Why? Or why not? o Plot your gm vs VGS curve for VDS = 10 V. Try to explain the variation you see in gm vs VGS. Make sure you include your hand calculated data points from the table. Do they agree with the measurements obtained using FETgm.vi? Why? Or why not? Question: o Suppose your JFET was put into a circuit that caused it to have a VGS = -1 V and a VDS = 10 V. An AC signal is added onto the gate having amplitude of 100 mV at 500 Hz. How large of a current amplitude would the JFET current source provide? (In other words: How large would gm*vgs be?) Conclusions: Type your conclusions for this lab.

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