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STA
STA
amey.hegde@wipro.com
Agenda
PRE-REQUISTES: Knowledge of Digital Design TOPICS COVERED : - Basic STA concepts - Basic Primetime Commands, Interpretaion of Primetime reports - Advanced STA (Mutliple clocks, Latches, OCV) - Setting up Primetime (Appendix 1)
Wireload models
RTL Coding
RTL Simulation/Verification
Synthesis
Wireload Models
Wire Loads Estimate interconnect length Statistical Analysis of Previously Routed Chips Predict the interconnect capacitance as a function of net fan-out and block size.
Wire Load Table Net Load Net Resistance
Net fanout
Net fanout
1 2
1 2
0.012 0.016
3
4
3
4
0.020
0.024
Outputs
Reports : The timing paths report which can be used for debugging.
D Q FF1
D Q FF2
OUTPUT
CLOCK
Each path has a startpoint and an endpoint Timing path Startpoints - Input ports, - Clock pins of flip-flops Timing path Endpoints - Output ports, - all input pins of flip-flops except clock pins
Setup time
Setup time: the time required for the data to be stable before the clock edge D1 Q1 FF1
0.4ns
Combo logic
D2 Q2 FF2
4.5ns
CLK CLK
setup violation
Launch Edge Capture Edge
D2
4.9
setup time
CLK
0 0.3 4.7 5
Hold time
Hold time: the time required for the data to remain stable after the clock edge D1 Q1 FF1 D2 Q2 FF2
0.3ns
CLK1
0.4ns
CLK2
CLK1
Launch Edge Capture Edge
CQ
D2=Q1
0.4 Hold violation hold time
CLK2
0.2
0.3 0.5
FF1
CLK
hold time
FF2
CLK
setup time
D2=Q1 Q2
CQ
CQ
100
Important!! In STA, Setup is checked at next edge and hold is checked at same edge
Setup Check
Setup check
D Q FF1
D Q FF2
CALCULATION: Arrival time (max) = clock delay FF1 (max) +clock-to-Q delay FF1 (max) + comb. Delay( max) Required time = clock adjust + clock delay FF2 (min) - set up time FF2 Slack = Required time - Arrival time (since we want data to arrive before it is required) clock adjust = clock period (since setup is analyzed at next edge)
Hold check
Hold check
.
D Q FF1
D Q FF2
CALCULATION: Arrival time = clock delay FF1 (min) +clock-to-Q delay FF1 (min) + comb. Delay( min) Required time = clock adjust + clock delay FF2 (max) + hold time FF2 Slack = Arrival time - Required time (since we want data to arrive after it is required) clock adjust = 0 (since hold is analyzed at same edge)
Header
Summary- Slack
Clocks
Slew or Transition time: Time taken for a signal to reach from 10% of VDD to 90% VDD
90%
Slew
10%
Period
Clocks
Jitter - Variation in period from clock source (PLL)
Insertion Delay delay from clock source to the clock endpoint Skew - Difference in arrival time at clock endpoints
FF1
clk
FF2
clock skew = clock insertion delay of FF1 - clock insertion delay of FF2
Clocks
Source latency and Network latency
Master Clocks
Virtual Clocks
Virtual Clocks
Source latency and Network latency
Block
D Q D Q D Q D Q
Input Delay
Output Delay
Timing Exceptions
STA tools assume single cycle timing for all paths in design single cycle timing means that data propogates to its destination in less than one cycle timing exceptions are used to override the default single cycle constraints. False paths Multicycle paths Max delay Min delay
max_delay=1ns
False Paths
False path
- any logically false path - any register to register path which you do not wish to constrain - these paths are excluded from timing analysis
Note:
Asynch resets are synchronized before giving to CLRZ (reset) pin of flip-flops
Gated clocks
Gated clocks
Clock gating Setup check Enable of the clock to be stable before clock assertion, to preserve the waveform Clock gating Hold check Enable of the clock to be stable after clock assertion, to preserve the waveform. Violation causes Glitch at the edge of the clock pulse. clipped clock pulse
Enable
A
Out
Z
Clock
Operating Conditions
Gate Delay depends on
input slew output load strength of the gate Voltage temperature
Sources of variation
process variation (P) Supply voltage (V) Operating Temperature (T)
Design corners
Best case (fast process highest voltage and lowest temperature) Worst case (slow process lowest voltage and highest temperature)
7 7
0 1.0
PROCESS
D E L A Y
7
2.3
7
3.0
VOLTAGE
D E L A Y
7
7
0 12 TEMPERATURE 5
TE
D Q QB
functional
Most functional paths are long paths that make meeting timing during worst case operating conditions a challenge. Some functional paths, and many test paths, are very short, such as this scan chain.
(350ps)
TI TE D Q
TE
D Q
(0 slack MAX)
Clk (300ps)
Clk (0ns)
QB
QB
Early mode timing needs to be aware of both minimum and maximum timing. Solution: Dont increase the loading of the Q output but use the unused QB output
On-Chip Variation
D Q QB
TEMP = 60
D Q QB
TEMP = 65
On-chip variation is minor differences on different parts of the chip within one operating condition.
On-Chip Variation
On-Chip variation (OCV)
delays vary across a single die due to variations in the maufacturing process (P), variations in the voltage (due to IR drop) and variations in the temperature (due to local hot spots etc.) This need to be modeled by scaling the coefficients
On-Chip Variation
OCV Derations
Timing analysis with on-chip variation. For cell delays, the on-chip variation is between 5 percent above and 10 percent below the SDF back-annotated values. For net delays, the on-chip variation is between 2 percent above and 4 percent below the SDF backannotated values. For cell timing checks, the on-chip variation is 10 percent above the SDF values for setup checks and 20 percent below the SDF values for hold checks.
pt_shell> read_sdf -analysis_type on_chip_variation my_design.sdf pt_shell> set_timing_derate -cell_delay -min 0.90 -max 1.05 pt_shell> set_timing_derate -net -min 0.96 -max 1.02 pt_shell> set_timing_derate -cell_check -min 0.80 -max 1.10
CRPR
Common path pessimism
It is possible to have common logic between min and max paths It is not possible to have two different delays simultaneously in a single gate or wire Common path pessimism removal removes common delays.
Primetime Report
Primetime slack report: Interpretation
-------------------------------------------------------------------------------------------------------------------------Point Incr Path -------------------------------------------------------------------------------------------------------------------------clock CLK (rise edge) 0.00 0.00 clock network delay (propagated) -> clock path delay of launch path (startpt) 1.40 1.40 FF1/CP (FD2) 0.00 1.40 r FF 1/Q (FD2) ->CLK to Q delay 0.60 2.00 f BUF1/y (BUF) -> combo delay upto the D pin of the endpt. register 3.20 5.20 f data arrival time 5.20 clock CLK (rise edge) -> includes Cycle adjust of 1 clock period 5.00 5.00 clock network delay (propagated) -> clock path delay of capture path (Endpt) 1.16 6.16 clock reconvergence pessimism -> after correction for CRPR 0.16 6.32 clock uncertainty -> post cts this is only jitter -0.10 6.22 FF2/CP (FD2) 6.22 r library setup time - 0.20 6.02 data required time 6.02 ---------------------------------------------------------------------------------------------------------------------------data required time 6.02 data arrival time -5.20 ---------------------------------------------------------------------------------------------------------------------------slack (MET) 0.82 Path slack = required time- arrival time = (6.02-5.20)=0.82
8 B (8ns)
0 1 2 3 4 5 6
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
D Q D Q
QB QB
The setup relationship is the closest distance between the launching clock edge (A) and the receiving clock edge (B)
0 B
0 1 2 3
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
D Q D Q
QB QB
The hold relationship is the closest distance between the launching edge (A) and the previous receiving edge (B)
Latches
Latches and Flip-Flops are both registers, or storage devices D
D Q
QB
Q B
D
0 1 2 3 4 5 6 7 8
Q
0 1 2 3 4 5 6 7 8
Time Borrowing
D Q G D Q
D Q G
a_reg
PHI b_reg 2
c_reg
10
15
20
If these were flip flops, timing would not be met at b_reg. With time borrowing, the middle latch can borrow time from the next stage and meet timing.
D Q G
D Q G
a_reg
PHI b_reg 2
c_reg
10
15
20
Q. Can time borrowing eliminate negative slack? No, the final data missed the active edge of c_reg.
D Q G
D Q
a_reg
PHI b_reg 2
c_reg
10
15
20
Q. Can time borrowing eliminate negative slack? No, c_reg is a flip-flop and the data misses c_regs edge
D Q G
D Q G
a_reg
PHI b_reg 2
c_reg
10
15
20
Yes, in fact there is extra time before the activating edge of c_reg.
D Q G
11
D Q G
a_reg
PHI b_reg 2
c_reg
10
15
20
A simple multimode scheme allows the timer to be aware of the propagation of both clocks in the same run.
This awareness enables single-pass implementation and optimization of both clocks and their associated timing paths.
scan SD
D Q QB
DATA_OUT
QB
TEST_EN TEST_CLK 1 FUNC_CLK
Define both TEST_CLK and FUNC_CLK Apply timing constraints for all I/O and scan ports with respect to appropriate clock Apply all other constraints as usual (drives, loads, slews, etc.) If multiple functional clocks can drive a given clock pin, choose the clock with the highest frequency and define that clock only
This applies only to the case where the same boundary clock pin might be driven by different clocks, depending on the mode.
Do not declare all paths from/to either clock to be false, (Avoid openended false path statements on clocks). Do not set constants that choose either test mode or scan mode (Do not set TEST_EN high or low).
scan SD
D Q QB
DATA_OUT
QB
TEST_EN TEST_CLK 1 FUNC_CLK
TEST_CLK
1 FUNC_CLK
PrimeTime must perform mode analysis (set the design in a mode), because it cannot propagate multiple clocks on a net. For PrimeTime runs, you need one additional constraints file for each mode (mode constraints file) to set the design in a mode.
For this simple example we need two files: test mode and func mode
The test mode constraints file has the command:
set_case_analysis 1 TEST_EN
The func mode constraints file has the command:
set_case_analysis 0 TEST_EN
Combinational Loops
U1
Z
D Q QB
U0
A Z B
D Q
QB
Most STAs cant leave combinational loops in the design, because a race condition will occur.
AT
References/Resources:
Magma STA training slides VSBU STA training ppt. Primetime user guide Primetime tutorial can be used for hands on
Appendix 1
Primetime
Primetime Flow:
Read and Link Designs and Libraries
Setup Files :
Primetime
Primetime
Specify the timing assertions (constraints) Define clock period,waveform,latency and uncertainty. Specify input and output port delays.
Specify timing exceptions specify multicycle path specify false path Specify minimum and maximum delays specify disabled arcs.
Primetime
Reading the Designs
Primetime reads following design formats Synopsys database files (.db) Verilog netlist files Electronic Data Interchange Format( EDIF) netlist files VHDL netlist files e.g : r ea d _d b ../ gt ech / cou n t er .d b r ea d _ver ilog ../ n et / cou n t er .v r ea d _ed if ../ ed if/ cou n t er .ed if r ea d _vh d l ../ n et / cou n t er .vh d l
Primetime
Defining operating conditions
ICs exhibit different performance under different operating conditions operating conditions contains process derating factor(P), supply voltage(V),ambient temperature and interconnect model type delay calculation is affected by the operating conditions