Challenges of 90nm Physical design

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Sophia Antipolis
8 - 9 Oct 2003
Session Title p 2
What do you get from the tutorial
Introduction to 90nm effect: Changing nature of delay, signal
integrity.
Recap on basic notions: Delay calculation, Parasitic prediction,
Floorplanning, Physical Synthesis
Limitation of current flow: Physical synthesis based.
New flow based on silicon virtual prototype
Signal Integrity
You will not become an expert in 90nm physical design but you
will have the background to start investigating this new
frontier.
Session Title p 3
90 nanometer design flow
Wire-Wire-Wire everywhere
Changing nature of Delay
Cross coupling
IR Drop
History of flow from 250nm to 90nm.
90nm flow Continuous convergence.
Session Title p 4
Wiring dominates nanometer design
Wiring delay exceeds gate delay at 180nm in aluminium process
and at 130nm in copper process.
Focus shifted from logic optimisation to wire optimisation
Session Title p 5
Changing nature of delay - 1 -
Physical effects introduce substantial delay: Signal
integrity, IR Drop.
Simplified model such as lumped capacitance are not
enough.
Lumped
capacitance
input 1
input 2
input 3
Session Title p 6
Changing nature of delay - 2 -
At 250 nm and above the primary wire capacitance is
due to coupling to electrical ground and is largely
proportionate to wire length.
Wire length is predicted based on netlist information
(wire load model) or on placement (steiner tree, global
routing estimates).
Substrate
Fringe
Session Title p 7
Reminder/Definition: Wire Load Model
Goal; Estimate capacitance before placement is known.*
Based on statistical data: capacitance depends on number of
instances in the netlist and net fanout.
Stored in look-up tables in the library or derived from
previous iterations.
Capacitance too big
Predicted capacitance
Fanout = 4
NetIist = 100K
SIow
Fast
capacitance too smaII
Capacitance pF
nets
Session Title p 8
Recap/definition: Routing estimates
Steiner tree:
minimum length tree
Global routing: Set of steiner trees
minimizing total wire length and
congestion.
Global routing computes the topology of each net on a coarse grid
(routing bin). The detailed routing (track assignment) is not know.
Primary goal is to compute wire length..
Global routing can predict wire length but cannot predict coupling effect.
Session Title p 9
Changing nature of delay: Cross
Coupling.
As geometries decrease, the primary capacitive coupling on a given wire
moves to its neighboring wires.
Capacitance depends on the local wire geometry and, in many cases, to
the actual signals.
Variation is +/- 30% for 1MM
wire and +80%/-60% for 3MM
wires.
Session Title p 10
Cross coupling conclusion
Placement based estimates steiner trees, global routing are not
accurate enough. Detailed routing is required to predict
performances.
Issues:
How can we get early access to detail routing.
How can we iterate fast enough when detailed routing is required.
Session Title p 11
Changing nature of delay: IR Drop
Resistance in the power and ground wire networks
create IR Drop.
VoItages depend on currents
of other ceIIs
Pad
Power suppIy
network consists
of wires of varying
sizes; they must be big
enough, but too big wastes area
Currents depend on driver type,
Ioads, and how often ceII is
switched
AIIowabIe
voItage
drop at pin
Session Title p 12
Changing nature of delay: IR Drop and
delay
An IR Drop from 1.7V to 1.6V is capable of producing delay
variation of 50 or more.
One study of designs at 180 nm showed that 20 of designs
failed on first silicon due to excessive IR Drop alone.
Conclusion: 90 nm flow should include a tool to compute IR
Drop and a delay calculator taking into account the IR Drop.
Session Title p 13
Recap: delay calculation
Timing verification is split into two components:
Delay calculator: computes delay between gate output and gate
inputs based on extracted RCs.
Static Timing Analysis engine: propagate the delay in the cells and
in the interconnect to check for timing violations.
90 nm DC such as Signal Storm takes into account:
IR Drop
Cross talk impact on delay.
STA tools such as Primetime, Buildgates read in an SDF
file the delay computed by the Delay calculator.
Session Title p 14
Delay Calculator flow
90 nanometer design flow.
Session Title p 16
What have we seen sofar
Delay is dominated by wires.
Delay is dependent on SI issues (cross coupling) and IR Drop.
Next foils will investigate the impact of the above on the
physical design flow and the physical implementation tools
Session Title p 17
Nanometer design flow.
Dominance of wire delays has significantly modified the flow in the
last 10 years.
250 nm and above:
Gates dominate delay. Wire delay can be estimated using wire load model. Synthesis
and place and route are two different steps.
180-130 nm:
Wire delay starts dominating overall delay. Better accuracy is needed in wire delay
estimation:
Placement and Synthesis merge (Physical Compiler, PKS) at the block level
Floorplanner to estimate top level wires.
90 nm and below.
Wire delay dominates the design. Wire delay depends on cross coupling
Performance is unknown before routing.
Introduction of tools and flow that generate wires as soon as possible (time to wire).
Session Title p 18
250 nm: Simplified DESIGN FLOW
RTL
Layout
Net||st
8ynthes|s
P|ace and Route
0 R 6
Equivalence
checking
Simulation
Simulation
Extraction
R.C
Timing Verification
Wire Load Models
Session Title p 19
180/130 nm: Floorplanning improves parasitic estimates
and constrains the place and route iterations.
Wire Load Models
are more accurate
in small blocks
Top level wires
topology
be estimated
Hard Macro
Soft Macro Soft Macro
Place and route iterations are
constrained by the Floorplan
reducing the chaotic effect and
improving the convergence.
Placement based
synthesis can handle
smaller blocks
Session Title p 20
180/130 nm Placement based synthesis
Parsing, Structuring Mapping
accept /reject
Route & Time
using fast router
Initial Placement
Optimization Transforms
restructure, clone, remap, buffer, etc
Incremental Placement
10

RTL Source Physical Constraints

Synthesis
Library
Physical
Library
(LEF)
Physical Constraints Timing Constraints
Place Place a,nd a,ndRoute Route
Detail Placement
Detailed routing
Timing Constraints
Session Title p 21
Nanometer design iterations:
~time-to-wire
Design methodology must minimize time to wire and full chip iteration time: Continuous
convergence methodology.
In nanometer design
physical synthesis is
used only on those
blocks that full chip
detailed routing
identifies as not
meeting timing.
Session Title p 22
Continuous convergence
Continuous convergence begins with an initial full chip
design representation with wires called silicon virtual
prototype (SVP).
SVP treats all aspects of the design: logic, timing, SI, IR
Drop, Electromigration, I/O and manufacturability.
SVP should have a one day turn around to allow design
teams to identify and prioritize performance and
manufacturing issues.
SVP is followed by a final chip implementation when all
design parameters and architectures have been finalized
and validated.
Session Title p 23
Continuous convergence
Signal Integrity
Session Title p 25
Overview
What is Signal Integrity(SI)?
Terms associated with Signal Integrity
Performance Vs. reliability/manufacturability concepts
General SI concepts
Crosstalk, IR Drop, Hot Electron
Electromigration, Wire Self Heat, Process Antenna, Metal Density
Approaches
Hierarchical Challenge
Routing Topologies
Floorplan Topologies
Overview
Session Title p 26
Performance, Reliability and Manufacturability
in Signal integrity
Performance
Crosstalk
IR Drop
Reliability
Hot Electron
Electromigration
Wire Self Heat
Manufacturability
Process Antenna Effect (PAE)
Metal Density
Overview
Session Title p 27
Impact of Noise on Delay
a1
|n
v|ct|m
v|ct|m
|mpact of No|se
on de|ay
de|ay w|thout
coup||ng
a1
|n
v|ct|m
Crosstalk increases delay
Session Title p 28
Impact of Noise on Functionality
Attacker
reset 1
cIk
d
q
1
0
v|ct|m
Session Title p 29
Crosstalk
Aggressor & Victim Relationship
Spatial
Proximity and Width of conductors
(Capacitance and resistance)
Coupling location distance from drivers
Failures Caused
Functional (Logic level change)
Timing (Setup/Hold)
Simple Definition:
Coupling of electric and magnetic
fields between conductors
GeneraI Concepts:Performance
Victim
Victim
Aggressors CoupIing
5 ns 15 ns 10 ns
20 ns
1 V
2 V
victim
(no coupIing)
aggressor
victim
(coupIing)
X-taIk
DeIay
Temporal
Signal slews and time of switch
Session Title p 30
Analysis and Avoidance
Analysis Requirements
Driver Strength
Routing topology and RCs
Timing Analysis to identify slew relationship and edge alignment
Victims net receiver noise margin
Avoidance
Separate victim from Aggressor
Shield Aggressor
Reduce victim slew, Increase aggressor slew
Change Temporal relationship
Session Title p 31
IR Drop
Voltage drop in supply lines from currents drawn by cells
Symptom: chip malfunctions on certain vectors
Biggest problem - what's the worst case vector?
VoItages depend on currents
of other ceIIs
Pad
Power suppIy
network consists
of wires of varying
sizes; they must be big
enough, but too big wastes area
Currents depend on driver type,
Ioads, and how often ceII is
switched
AIIowabIe
voItage
drop at pin
Session Title p 32
IR-Drop
Failures Caused
Functional (Logic level change) due to noise margin reduction
Timing Setup and Hold due to circuit slow down or speed-up
IR drop in power grid will create variations in delay across the chip
Performance of a chip roughly varies by 7-9% when v
dd
is varied by 10%
Affect clock skew in the clock network
Simple Definition:
Resistance in power grid causes a
reduced supply voltage at the delivery
point.
'V = IR
V
dd
R
V
ss
R
I
V
dd
- 'V
C
L
DeIay Vs SuppIy VoItage
0.5 ns 1.5 ns 1 ns
1 V
2 V
V
T
SuppIy
VoItage
Variation
DeIay
Variation
Session Title p 33
Analysis and Avoidance
Analysis Requirements
IR Drop characterization of cells
Power supply network RCs extraction
Estimation of current drawn by each cell
Supply voltage calculation at each cell
Avoidance
General estimation of power network using average current drawn per cell and
row utilization.
Network resistance reduction (adding via cuts and increasing or tapering wire
width)
Establishing max transition time for whole chip.
Insertion of decoupling caps.
Session Title p 34
Hot Electron Effect on Devices
Failures Caused
Functional
Eventual device failure
Timing
Threshold and mobility shifts.
Device operates out-of-spec (timing characteristics change)
Simple Definition:
Process are reducing transistor
feature sizes (W/L) faster than supply
voltage. Electrons in the channel are
damaging the drain and gate oxide.
+++
+++
Oxide and/or interface
is damaged here
Impact ionization
occurs here
Session Title p 35
Analysis and Avoidance
Analysis Requirements
Fluence cell characterization (Flux of injected hot e- [coulomb/m
2
])
Chip lifetime estimation
Number of transitions per cycle
Avoidance
Upsize driver (i.e., improve slew)
Insert buffer (i.e., reduce load)
Process control (Proportional reduction of supply voltage with feature size.)
Session Title p 36
Electromigration
Failures Caused
Power distribution
Specified voltage levels are not supplied to cells
Functional
Logic level change due to noise margin reduction
Circuit inoperable due to power structure breakage.
Timing Setup and Hold due to circuit slow down
Simple Definition:
Constant DC current on high
Resistance segments causes
malformation and/or breakage on
power interconnect.
Session Title p 37
Analysis and Avoidance
Analysis Requirements
Characterization of cells current consumption
Power supply network RCs extraction
Wire DC and peak current densities based on the current consumption of each
cell and the resistance of the power grid.
DC current densities are compared to the process limits.
Avoidance
General estimation of power network using DC or average DC current drawn
per cell and row utilization.
Network resistance reduction (adding via cuts and increasing or tapering wire
width).
Session Title p 38
Wire Self Heat
Dependencies
Metal composition
Signal frequency
Wire sizes
Slew rates
Amount of capacitance driven
Simple Definition:
Voltage drop with AC current causes
wire to heat up as pulses go through it.
MetaI
Failures Caused
Signal transmission effectiveness
reduction
Chip failure due to broken wire.
Oxide
Session Title p 39
Analysis and Avoidance
Analysis Requirements
Characterization of cells current consumption
Power supply network RCs extraction
Wire AC current densities based on the current consumption of each cell and
the resistance of the wire.
AC current densities are compared to the process limits.
Avoidance
Net resistance reduction (Wider routes, top layers, etc.)
Reduce load (Insert buffers/Net splitters)
Set global Design Rules (I.e. Max Load, Max Fan Out)
Session Title p 40
Process Antenna Effect (PAE)
Failures Caused
Shift the transistor threshold voltage
Oxide breakdown
Functional
Logic level change due to noise margin reduction
Circuit inoperable due to damaged gate
Timing Setup and Hold due to changes in circuit timing characteristics
Simple Definition:
During fabrication Electric charges
are accumulated in wires connected
only to input pins. It could get
discharged through the gate damaging
the gate oxide.
p-substrate
FOX
M1
M2
Poly
N+ N+
N+ N+
Poly
Session Title p 41
Analysis and Avoidance
Analysis Requirements
Metal Area to Gate Area ratio
Metal Side Area to Gate Area ratio
Layer Only Vs Cumulative
Avoidance
Layer hoping
Diode insertion during routing
Diode embedded in cell
Buffer/Repeater insertion right on the pin inside the block
Force pin assignment to last metal on critical nets.
Antenna Approach
RationaIe and Impact
Session Title p 42
Failures Caused
Manufacturing
Coves and bumps formed on metal and oxide causing optical un-alignment.
Timing and functional
Wire RC characteristics affected due to Metal thickness not distributed as specs.
Metal Density
Simple Definition
Percentage of metal required per unit
area of the die. Specified per layer. For
example: 20 of M3 in 50 um
2
Session Title p 43
Analysis and Avoidance
Analysis Requirements
Metal utilization per square area.
Avoidance
Metal fills are added to satisfy minimum density rules.
Wires are split or slotted to satisfy the maximum density rules.
Fixed as a post process of the placed and routed database or the GDSII
database.
Started to be fixed in the place and route environment due to it implications
on RC extraction, Timing Analysis, Signal Integrity, etc.
Session Title p 44
Conclusion
90nm flow: Wire, Wire, Wire
Behavior, Performance, Yield : you cannot ignore Signal
Integrity anymore.
Retooling is necessary to go from 130nm to 90nm.
This presentation did not address Mixed-Signal issues often
present in 90nm due to the high level of integration.