MULTISTAGE AMPLIFIER

Cascaded Connection
Output of one stage is connected
to the input of another stage.

Amplifier 1
Gain = A
V1

V
in 1

V
o 1


Amplifier 2
Gain = A
V2

V
o 2


Overall gain A
V
= V
O2
/ V
in 1
= A
v1
- A
V2

Cascaded BJT Amplifier
V
1o

C
s1

Q
1

C
1

R
E1

R
2

V
i

R
C1

V
CC

R
1




Gain A
V1
=
e
L C o
r
R R
V
V
1 1
1
1
||
=
C
s2

C
2

Q
2

R
E2

R
4

R
C2

V
CC

R
3

V
2o




Gain A
V2
=
e
L C
o
o
r
R R
V
V
2 2
1
2
||
=
V
i

b
R
1

I
b2

r
i2

R
2

|
1
I
b1

c
I
c1

V
1O

R
C1

R
3

R
4

e
I
b1

r
i1

c
|
2
I
b2

V
2O

R
C2

C
s1

V
i

Q
1

C
1

V
1O

R
2

R
1

R
C1

V
CC

R
E1

Q
2

C
2

V
2O

R
4

R
3

R
C2

V
CC

R
E2

C
s2

e
R
L

e1
e2 2 4 3 C1
v1
r
r * || R || R || R
A =
e2
C2
v2
r
R
A =
e2
L C2
v2
r
R || R
A =
v2 v1 v
A * A A gain, Overall =
V
i

b
R
1

I
b2

r
i2

R
2

|
1
I
b1

c
I
c1

V
1O

R
C1

R
3

R
4

e
I
b1

r
i1

c
|
2
I
b2

V
2O

R
C2

e
R
L

e1 1 2 1 i
r * * R * R Z Impedance, Input =
o c2 o
r * R Z Impedance, Output =
20f
V
i

Q
1

10f
V
1O

4.7K
15K
2.2K
+20V
1K
Q
2

C
2

V
2O

6.8K
22K
1.5K
20V
1K
20f
Draw the (i) Input and (ii) output voltage waveshape for
different values of V
i
(a) 25V (b) 1mV (c) X mV, where X is
last two digits of your Roll No.
Cascaded FET Amplifier
C
s1

Q
1

C
i

R
s1

R
G1

V
i

R
D1

V
DD

A
V1
= -g
m1
R
D1


A
V2
= -g
m2
R
D2


Overall gain A
V1
-A
V2
= (-g
m1
R
D1
)(-g
m2
R
D2
)



Input Impedance Z
in
= R
G1


Output Impedance Z
O
= R
D2

C
s2

Q
2

C
2

R
s2

R
G2

V
o1

R
D2

V
DD

V
o2

Darlington Connection

Overall | = |
1
|
2

Q
1

Q
2

Two transistors are connected in
such a way that emitter current of
one is fed to the base of another, so
that the overall current gain is the
product of their individual current
gains.
It is also known as superbeta
transistor
I
E1
= (1+ |
1
) - I
B1

I
B1

I
E1

I
E2

I
E2
= (1+ |
2
) - I
B2

I
E2
= (1+ |
2
) - (1+ |
1
) - I
B1

I
E2
~ |
2
- |
1
- I
B1

2N999 npn darlington transistor
V
BE
= 1.8V at I
C
= 100mA

D
= 4000 at IC = 10mA

D
= 7000 at IC = 100mA
Maximum
D
= 70,000 at IC = 100mA
DC bias of Darlington Circuit
R
E

R
B

V
CC

|
D

I
B

I
E

I
C




E D B
BE CC
B
R R
V V
I
| +

=
V
BE




( )
B D B D E
I I I | | ~ + = 1



BE E B
V V V + =



E E E
R I V =
DC bias of Darlington Circuit
390R
3.3M
18V
|
D

I
B

I
E

I
C

A 2.56
390R * 8000 3.3M
1.6 18
I
B
=
+

=
V
BE

20.48mA 2.56. * 8000 I
E
= =
6V . 9 6 . 1 8 = + =
B
V
8V 390R * 20.48mA V
E
~ =
V
BE
= 1.6V

D
=8000
AC analysis of Darlington Circuit
V
i

R
E

R
B

V
CC

|
D
= 8000


V
BE
= 1.6V


I
b

I
E

I
C

C
i

C
i

V
O

I
b

R
E

r
i

R
B

V
i

V
O

|
D
I
b

I
i

AC Input Impedance of Darlington
Circuit
I
b

R
E

r
i

R
B

V
i

V
O

|
D
I
b

I
i



i
o i
b
r
V V
I

=
( )
E b D b o
R I I V | + =



( ) | | ( )
E D i b E D i b i
R r I R r I V | | + ~ + + = 1



( )
E D i B
i
i
i
R r R
I
V
Z | + = = ||

D
=8000
r
i
= 5K
AC Current Gain of Darlington Circuit
b D b D b o
I I I I | | ~ + =
( )
i
B E D i
B
b
I
R R r
R
I
+ +
=
|
( )
E D i b i
R r I V | + ~



i
o
i
I
I
A =
I
b

R
E

r
i

R
B

V
i

V
O

|
D
I
b

I
i

I
o

i
B E D
B
b
I
R R
R
I
+
~
|
E D B
B
D
i
b
b
o
i
o
i
R R
R
I
I
I
I
I
I
A
|
|
+
= = =
AC Output Impedance of Darlington Circuit



o
o
o
I
V
Z =
R
B

r
i

R
L

V
O

|
D
I
b

I
b

V
S

R
E

Z
O

r
i

V
O

|
D
I
b

R
E

I
O

b D
i
o
E
o
o
I
r
V
R
V
I | + =
|
|
.
|

\
|
+ =
i
o
D
i
o
E
o
o
r
V
r
V
R
V
I |
i
D
i E
o
o
o
r r R
I
V
Z
|
+ +
= =
1 1
1
AC Voltage gain of Darlington Circuit



i
o
V
V
V
A =
( )
E b D b o
R I I V | + =
r
i

V
O

|
D
I
b

I
b

V
S

R
E

o i b i
V r I V + =
( )
E D E i b i
R R r I V | + + =
( )
b E D E o
I R R V | + =
( )
( )
E D E
E D E i
i
o
R R
R R r
V
V |
|
+
+ +
=
( )
( )
1 ~
+ +
+
= =
E D E i
E D E
i
o
V
R R r
R R
V
V
A
|
|
Summery of Darlington connection
Super beta transistor, |
D
= |
1 -
|
2.

High current gain, can amplify very small signal.
Increased input impedance.
Reduced output impedance.
Unity voltage gain.
CMOS Circuit
Complementary Metal Oxide
Semiconductor Field Effect Transistor
V
DD

V
i

V
o

pMOS
nMOS
S
S
D
D
G
G
V
GS
= -5V
V
GS
= 0V
V
i
= 0V
V
o
= 5V
V
DD
= 5V V
DD

pMOS
nMOS
S
S
D
D
G
G
V
GS
= 0V
V
GS
= 5V
V
i
= 5V
V
o
= 0V
V
DD
= 5V
CMOS is used as
an inverter
Current source
R
L
= 1O
I
S
= 10A
I
L
= 10A
R
L
= 2O
I
DSS
= 8 mA
V
P
= - 5 V
R
L
=1K
V
DD
=10V
I
L
= 8 mA
R
L
= 2K
V
DD
= 24V


V
O
= ?
2
1
|
|
.
|

\
|
=
P
GS
DSS D
V
V
I I
R
L
= 5K
BJT Current source
I
C

R
E

V
B

I
E
R
2

-V
EE

R
1

V
CC

R
L

( )
EE B
V
R R
R
V
+
=
2 1
1
7 . 0 =
B E
V V
C
E
EE E
E
I
R
V V
I ~

=
) (
BJT - Zener Current source
V
CC

R
L

C
E
BE Z
E
I
R
V V
I ~

=
I
C

R
E

V
B

I
E

V
Z

-V
EE

R
1

Current Mirror Circuit
B C X
I I I 2 + =
V
CC

R
X

I
C

Q
2
Q
1

I
X

I
C

I
E

I
E

I
B
I
B

2I
B

| |
E E
B
I I
I ~
+
=
1
E C
I I ~
|
E
E X
I
I I
2
+ =
E E X
I I I ~
|
|
.
|

\
| +
=
|
| 2
V
R
L

I
L

V1
R
L1

I
L1