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The 2004 ITRS

Assembly and Packaging Roadmap


Joe Adam TWG Co-Chair

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14 July 2004 ITRS Summer Conference

Key Packaging Chapter Contributors


Ryo Haruta Renesas Dan Evans Palomar Tech Enboa Wu ITRI/NTU Shoji Uegaki Kyocera Kuniaki Takahashi Toshiba Hisao Kasuga NEC Coen Tak - Philips Mark Bird - Amkor Bill Bottoms - 3MTS Steve Adamson - Asymtec Chi Shih Chang SMS Bill Chen ASE Mahadevan Iyer - IME Bernd Roemer - Infineon Henry Utsunomiya ICT Jurgen Wolf IZM Joe Adam Skyworks Rainer Kyburtz - ESEC Jack Fisher - IPC George Harman NIST Chuck Woychik Plexus Sanjay Dandia Philips Keith Newman Sun

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14 July 2004 ITRS Summer Conference

Near Term Industry Challenges


We need to close the gap between semiconductor interconnect density and next level substrate density
Both Organic and Ceramic substrate density is improving but not as fast as silicon I/O density Higher temperature capability to support lead free solder in high density organic substrates Low cost embedded passives

The impact of BEOL and Cu/low K on packaging


Direct wirebond to Cu or improved barrier systems for bondable pads Improve interfacial adhesion of dielectrics Integrated fab/packaging process development, reliability, and test criteria to identify and resolve interaction problems early in the technology development cycle

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14 July 2004 ITRS Summer Conference

Near Term Industry Challenges


Tools and methodologies to address chip and package codesign
More efficient mixed signal co-design and simulation for chip and package within the same environment RF requirements More accurate thermal and mechanical simulation of complex package microstructures, including materials data

Assembly equipment productivity is not improving fast enough to meet package cost improvement requirements Reliability degradation due to electromigration in lead free and other package metallurgies

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14 July 2004 ITRS Summer Conference

Long Term Industry Challenges


Small high frequency, high power density, high pin count die Very high chip I/O density which require reliable bumpless connections to meet thermal and electrical performance requirements New devices and materials (organic, MEMS, nanostructures, optical, biological) which require new packaging technologies System level design capability to integrate semiconductor, passive, interconnect and new device technologies in 3 dimensions 450 mm wafer technical issues ( thinning, wafer level packaging, etc.)

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14 July 2004 ITRS Summer Conference

Subcontract Package Cost Trends


Package Type Low cost Cost Performance High Performance High Reliability Minimum Cents Per Pin for Subcontract Packages 2004 2005 2006 2007 2008 0.3 - .56 .751.30 1.98 .3 - .53 .711.24 1.88 2009 2010 0.27 - .5 0.26 - .48 0.25 - .45 0.23 - .43 0.22 - .41 .671.17 1.78 .641.11 1.69 .611.05 1.61 .581.00 1.52 .55.96 1.45

0.363.20 0.322.88 0.292.60 0.262.33 0.232.11 0.212.00 0.201.90

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14 July 2004 ITRS Summer Conference

System In Package Technology Requirements


Year of Production Digital networks- max I/O RF products - max I/O Memory products - max I/O Max number of stack die Max number die in Module Minimum Component size in. Die Pad pitch - wirebond Die pad pitch - flipchip Embedded Passives in Laminate Embedded Passives in Ceramic MSL Level Mx Reflow temp C 6 10 0201 40 150 L 7 12 0201 35 130 L 8 12 8 12 8 12 8 12 8 12 8 12 8 12 8 12 8 12 8 12 2004 2600 150 2005 2900 200 2006 3000 200 2007 3200 200 2008 3500 200 2009 3500 200 2010 3500 200 2012 3500 200 2013 3500 200 2015 3500 200 2016 3500 200 2018 3500 200

01005 01005 01005 01005 01005 01005 01005 01005 01005 01005 35 130 CL 30 120 CL 30 110 CL 25 100 CL 25 90 CL 25 90 CL 25 80 CL 25 80 CL 25 70 CL 25 70 CL

R, L, C R, L, C R, L, C R, L, C R, L, C R, L, C R, L, C R, L, C R, L, C R, L, C R, L, C R, L, C 2a 260 2 260 2 260 2 260 2 260 2 260 2 260 2 260 2 260 2 260 2 260 2 260

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14 July 2004 ITRS Summer Conference

Package Materials Requirements


Materials Challenges
Wirebond Underfills Thermal Interfaces Materials Properties Molding Compound

Issues
Materials that enable 20 micron pitch without wire sweep, barrier metals for Cu wirebond pads to reduce intermetalic Ability to support 100 pitch on large die, reduce stress on low-K and compatibility with lead free reflow Increased thermal conduction, improved adhesion, higher modulas for thin applications Methodology and characterization database for frequencies above 10 GHz, Low modulas materials that reduce stress on low- wafer structures with low miosture absorption for high temperature lead free applications

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14 July 2004 ITRS Summer Conference

Package Materials Requirements


Leadfree Solder Flip Chip Materials Die attach solder for T j >200C Rigid Organic substrates Flexible Organic Substrates Embedded passives Solder and UBM the supports high current density and avoid electromigration No feasible solution seen Lower loss dielectric, lower T CE, and higher T g at low cost Lower T CE and improved metal adhesion Improved high frequency performance of dielectrics with K above 1000 High reliability, better stability resistor

LT CC

materials. Ferromagnetics for sensor and MEMs applications Low shrink dielectric and lower dielectric constant for high frequency application

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14 July 2004 ITRS Summer Conference

Die to Package Interconnect Requirements

Table 96 Chip-to-next-level Potential Solutions


Year of Production Technology Node Chip Interconnect Pitch (m) WAS Wire bondball 2004 hp90 35 40 25 30 35 35 150 30 35 20 30 30 30 130 25 35 20 25 30 30 130 2005 2006 2007 hp65 25 30 20 25 25 25 120 20 30 20 25 25 25 110 20 25 20 20 25 25 100 2008 2009 2010 hp45 20 25 20 20 20 20 20 25 20 20 20 20 90 2012 2013 hp32 20 25 20 20 20 20 20 25 20 20 15 15 80 2015 2016 hp22 20 25 20 20 15 15 20 25 20 20 15 15 70 2018

IS WAS Wire bondwedge IS WAS T AB* IS WAS Flip chip area array*

DRAFT - NOT FOR PUBLICATION

14 July 2004 ITRS Summer Conference

Crosscut issues
BEOL and low K/Cu integration into packaging Wafer Level packaging impact on interconnect Thinned die issues (test, FEOL) New device types and structures impact on packaging Design and Simulation (SIP, RF, etc.)
DRAFT - NOT FOR PUBLICATION 14 July 2004 ITRS Summer Conference

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