GMRIT Nanoelectronics Workshop

GMRIT-Nanoelectronics
Dr. V. Ramgopal Rao

Professor
Department of Electrical Engineering
Indian Institute of Technology, Bombay
Powai, Mumbai-400076
Email: rrao@ee.iitb.ac.in
Web: http://www.ee.iitb.ac.in/~rrao
Nanoelectronics Nanoelectronics-- Top Down Scaling Top Down Scaling
The Technology trends & research opportunities The Technology trends & research opportunities
What is expected ?
Power
0
0
Design Time
Cost
0
Complexity

0
Delay
Size 0
VLSI Design
VLSI CAD Tools
Technology & Fabrication
Materials Science
Physics
Chemistry
Modeling and Simulation
Characterization
Testing
Areas of Microelectronics
World Semiconductor Industry World Semiconductor Industry
Source: Dataquest
US $250
Billion
Applications of MOS Transistors Applications of MOS Transistors
Inverter
(a) Multiplexer System
(b) Addressable array
(Memory or Display)
Amplifier
Impedance Transformation
Variable attenuator
Variable phase shifter
Oscillator
MOS Capacitors
Metal can be metal,
or more frequently
heavily doped poly-Si
Oxide is usually
silicon dioxide,
but can be some
other high k
dielectric
Semiconductor is
usually Si , but can
be SiGe, SiC
Basic MOS Structure
MOSFET Operation Linear Region
V
DS
<
V
GS
-V
T
MOSFET Operation Saturation Region
NMOS Transistor Equations
So
This is the linear region of operation
For V
DS
> V
GS
-V
T
This is the saturation region of operation
( )
(
=
V V V V I
2
DS DS T GS
2
1
L
W
C
ox
D
( )
(
(
=

2
T GS
L
W
C
V V
I
2
ox
D
MOS Transistor Output
Characteristics
From S. M. Sze, Physics of Semiconductor Devices, John Wiley (1981)
MOS Transistor Subthreshold
Characteristics
Subthreshold swing ~ 60 - 100 mV/decade
( )
(

=
nkT
q
Kexp
I
D
V V T GS
Scaling Scaling
W=0.7, L=0.7, T
ox
=0.7
=> Lateral and vertical dimensions reduce 30 %
Area Cap = C = 0.7 X 0.7 = 0.7
0.7
=> Capacitance reduces by 30 %
Die Area = X x Y = 0.7x0.7 = 0.7
2
=> Die area reduces by 50 %
V
dd
=0.7, V
t
=0.7, T
ox
=0.7, I=(W/L) (C
ox
)(V-V
t
)
2
= 0.7
T= C x V
dd
= 0.7, Power = CV
2
f = 0.7 x 0.7
2
= 0.7
2
I 0.7
=> Delay reduces by 30 % and Power reduces by 50 %
= 0.7
Technology Technology -- Then and Now Then and Now
1981 2000 RATIO
Technology p-well
CMOS
Dual Well CMOS
Gate Oxide 40 nm 2 nm 20X
Poly Dimension 2.5 m 0.12 m 20X
Metal Layers 1 6
SRAM-Density

Cell Area
Access Time
4 K

1000 m
2

40 nS
16 M

5 m
2

1 nS
4000X

200X
40X

November 2000 Pentium 4 released with
clock speed: 1.5 GHz
Number of transistors: 42 million
Technology Scaling
GATE
SOURCE
BODY
DRAIN
Xj
Tox D
GATE
SOURCE
DRAIN
Leff
BODY
Dimensions scale down
by 30%
Doubles transistor density
Oxide thickness scales
down
Faster transistor, higher
performance
Vdd & Vt scaling Lower active power
Technology has scaled well, will it in the future? Technology has scaled well, will it in the future?
Transistor Count Trend
From S. E. Thompson, Sub-100 nm CMOS, IEDM 1999 Short Course
Minimum Feature Size Trend
Microprocessor Frequency Trend
Challenges Challenges--CMOS Scaling CMOS Scaling
Meikei Ieong, IBM
SIA Roadmap
Outline
CMOS Power Challenges
Possible Solutions
Technology approaches
Circuit approaches
System level approaches
Outline
Possible Solutions
Circuit approaches
Technology Scaling
GATE
SOURCE
BODY
DRAIN
Xj
Tox D
GATE
SOURCE
DRAIN
Leff
BODY
Dimensions scale down
by 30%
Doubles transistor density
Oxide thickness scales
down
Faster transistor, higher
performance
Vdd & Vt scaling Lower active power
Technology has scaled well, will it in the future? Technology has scaled well, will it in the future?
Transistor Integration Capacity
0.001
0.01
0.1
1
10
100
10 5 2 1 0.5 0.25 0.13
T
r
a
n
s
i
s
t
o
r
s

(
M
i
l
l
i
o
n
)
Technology (m)
Million Tr
On track for 1B transistor integration capacity On track for 1B transistor integration capacity
Is Transistor a Good Switch?
On
I =
I = 0
Off
I = 0
I = 0
I 0
I = 1ma/u
I 0
I 0
Sub-threshold Leakage
Drain Induced Barrier Lowering (DIBL)
Channel Length Modulation
Channel Length Modulation
Short-Channel Effects
Velocity Saturation
SCE SCE--Gate Oxide Scaling Gate Oxide Scaling
L=150 nm
L=70 nm
Gat e Oxi de Thi ckness ( nm)
0 1 2 3 4 5 6 7
0
50
100
150
200
250
300
350
D
I
B
L

(
m
V
/
V
)
D
I
B
L

(
m
V
/
V
)
Short-channel effects
Drive Current
Circuit Performance
Manufacturability
Reliability
The success of silicon is
because of SiO
2
Hot-Carrier Effects in MOS Devices
Challenges Challenges--CMOS Scaling CMOS Scaling
Meikei Ieong, IBM
Statistical Dopant Fluctuations
25 nm channel MOSFET will have an intrinsic V
T
uncertainty of about
10/W
1/2
mV/m
1/2
, where W is the width of the FET. May be
tolerable for logic, which tends to be wider and less dense, but may prove
problematic for SRAM, where the width is usually minimized. The maximum
variation on a chip for such cases can exceed 6o or 250 mV.
-1999 IBM paper in VLSI Tech Symp
Sub-threshold Leakage
Sub Sub--threshold leakage increases exponentially threshold leakage increases exponentially
Assume:
0.25m, I
off
= 1na/
5X increase each generation
at 30C
S.Borkar, DAC 2004
SD Leakage Power
SD leakage power becomes prohibitive SD leakage power becomes prohibitive
Intel
Gate Leakage Power
If Tox scaling slows down, then Vdd If Tox scaling slows down, then Vdd
scaling will have to slow down scaling will have to slow down
Leakage Power
Leakage power limits Vt scaling Leakage power limits Vt scaling
A. Grove, IEDM 2002
The Power Crisis
Business as usual Business as usual is not an option is not an option
Power Extrapolation
IEDM 2003
Markets with More Restrictive I
off
Market I
off
Nominal
Reason
Desktop <~100nA/m P
Active
Mobile market <~3nA/m P
Standby
Hand held <~100pA/m Deep Sleep
DRAM <~10pA/m Refresh/C
Store
V
CC
/V
T
trend for Intel's process technologies
Circuit and Device Interactions
Way to go :Dual V
T
and
DTMOS
Outline
Possible Solutions
Circuit approaches
AMD Technology Development
Power Challenges-Possible Technology
Solutions
Processes/ Materials (FEOL &
BEOL processes)
Device Structures
Novel Device Operation
High-K Gate Dielectrics
Metal gates
Work-function Engineering
Ultra Shallow S/D Junction Formation
Salicide Technologies
Elevated (Raised) Source/Drain (Epitaxy)
Low-K Dielectrics
Metal Barriers & Cap Layers
Novel Processes/Materials
Gate Leakage
IBM Data
High-K with metal gate by 2007 for 45 nm node
.Intel (Nov 2003)
JVD nitride MNSFETs JVD nitride MNSFETs
First First time time demonstration demonstration of of MNSFETs MNSFETs down down to to
100 100 nm nmchannel channel lengths lengths
Detailed Detailed interface interface characterizations characterizations
0.0 0.5 1.0 1.5
0
1x10
3
2x10
3
3x10
3
4x10
3
1.0
0.0
0.25
0.5
0.75
VGT (V)
Oxide
JVDNitride
W/L=10/0.1(m)
I
D

/

C
o
x

(
c
m
2

V
/
s
e
c
)
VD (V)
0.085 0.090 0.095 0.100
0
2
4
6
8
10
t=1000s
ISUB=41 A
W/L=10/0.1 (m)
VG=VD/2
Stress
Oxide
JVD Nitride
A
N
i t
x

1
0
1
2

(
c
m
2
)
DISTANCE ALONGTHECHANNEL(m)
VLSI Tech Symposium, Kyoto, Japan, 1999
IEEE Tran. on ED, Apr 2001
Current Status- High K
Toshiba, IEDM, Dec 2003
TaN gate
NUS, Singapore
UT Austin
IEDM, Dec 2003
Fringing Effects in High-K Transistor
K
gate
= 3.9, T
phy
=1.5nm K
gate
= 100, T
phy
=77nm
Gate Gate Spacer Spacer Spacer
Spacer
Fringing increases with increase in physical
thickness of the gate dielectric
Not to Scale
L
G
=70nm
Boron Penetration Issues - Poly Gate
1999 VLSI
Technology
Symposium
Metal Gate Technologies
Why not Poly-Si ?
Poly Depletion (insufficient activation)
Boron Penetration (ultra-thin oxides)
High-K Dielectrics (incompatible)
V
T
adjustment (with
ms
)
V
T
=V
FB
+(Q
B
/C
ox
)+2 +
B
Low sensitivity of V
T
to doping changes!
TiN Gate - TiO
2
Gate Dielectric (K=20-30)
CVD - more common (Carbon contamination)
Recently, direct oxidation of Ti
In RTP with 100 % O
2
SiGe Gate for reducing the poly-depletion problems
UC Berkeley
Low Temp Activation
and lower resistivity
for the P+ poly SiGe films
compared to Poly-Si
Advanced Gate Electrode
Dual Metal Gates for CMOS
u
ms
values for Ru and Ru-Ta alloy
On SiO
2
and HfO
2
/SiO
2
UC Berkeley-Molybdenum implanted with
nitrogen can show a large workfunction shift
NCSU, 2003
Mid-gap Gate Materials (SiGe)
Excellent g
m
for p-MOSFETs
Counter doping required to adjust Vt
for n-channel ; buried channel operation
Source/Drain Engineering
Laser thermal activation for
50 nm gate lengths
Heat the sample beyond the melting point of Si for a
short period of time in the order of nanoseconds,
which significantly enhances the solubility without
appreciable diffusion.
Hitachi, Japan, IEDM 2003
Plasma Immersion Ion Implantation
High throughput (400X for 300 mm wafers)
Low Machine cost
Ultra-shallow doping profiles due to
low implantation energy
Room Temp. operation
Compatibility to CMOS
Particularly suitable for p-MOSFETs
Plasma Implantation Induced Damage
Charging Damage
Occurs when there is imbalance
in electron and ion currents
Wafer surface gets charged to
a potential,causing a gate to
substrate potential difference (Vgs)
If Vgs is sufficiently large, FN
current begins to flow through
the oxide
This current creates traps/interface
states,and degrades oxide quality
Charging damage is dangerous, because it is cumulative in nature !
Occurs during pattering of interconnects
Silicides
CVD Cobalt process as against the PVD Cobalt for improved step coverage
Novel CVD-cobalt process with CCTBA (DiCobalt HexaCarbonylt-Butylacetylene)
precursor to avoid the formation of thick interfacial oxide on Si.
Samsung, Korea, Dec 2003 IEDM
Elevated (Raised) Source/Drain
Pre-bake before the
SEG is the critical
step
Elevated (Raised) Source/Drain
IBM, IEDM, Dec 2003
AMDs Next Generation Transistor
High-K Gate Dielectrics
Metal gates
Work-function Engineering
Salicide Technologies
Elevated (Raised) Source/Drain (Epitaxy)
Low-K Dielectrics
Metal Barriers & Cap Layers
Novel Processes/Materials
BEOL
ULSI Metallization Schemes
Tungsten (W) is used to for contact hole filling (via plugs or contact studs).
Decomposition of WF
6
is used for W deposition. A barrier metallic glue film is
normally used to inhibit the diffusion of fluorine to silicide or silicon surface, and
for good adhesion.
Deposit blanket W by Sputtering and then planarize the metal by
Chemical-Mechanical Polishing (CMP).
(W)
Reflow Al plugs is an
active research area for
some low cost products.
Damascene process is
used for interconnects
Aluminum Interconnect Patterning
Lift-Off Subtractive Etch
Lift-off avoids metal etch, increasing the pattern flexibility, but has limited
extendibility for sub 0.5 m feature sizes.
Deposit sequentially aluminum alloy, use the same film to fill contacts and define interconnects.
Damascene Process
Damascene Conventional
Adv. of Damascene:
Eliminates the metal
etch process. So alloy
metals can be used.
Works well with W,
Al alloys, Cu and Ag.
Multi-Level Metal Interconnects
Pentium II uses five levels of metal interconnects
Refractory metals are used as first level metal because of their process and thermal
thermal stability, and Al is used for upper-level metals (lower resistivity)
Schematic of a five level interconnect system
Low-k inter-level dielectrics (ILD)
an active area of intense research.
Currently used ILD: CVD-TEOS
based oxides. Fluorine is
incorporated to reduce the dielectric
constant.
Planarization-Why?
The demand for increasing metal levels calls for ILD planarity.
ILD planarization serves two purposes:
(i) to provide a smooth surface for good metal step coverage
(ii) to provide a flat-enough surface, within the lithography depth of focus (for
patterning of contact vias and metal wires)
No planarization
Smoothing
Partial planarization
Local planarization
Global planarization
Chemical-Mechanical Polishing (CMP)
Polishing pad
Used for ILD planarization, and useful for polishing of metal in W plug formation.
Polishing slurry consists
of colloidal silica
suspended in KOH
solution
R= K
p
p v,
R is rate of removal, p is applied pressure,
v is relative velocity between the wafer and
polishing pad, K
p
is the proportionality constant
(known as Preston coefficient, units (pressure)
-1
)
=> the process is also chemical, not purely mechanical
Preston Equation
n 6-8 layers of metal
n Vias and wires manufactured at same time (dual damascene)
n Top levels are thicker for power distribution
n Interlayer dielectrics are not all
Interconnects
Interconnects Will Limit Performance
M.Bohr, TED 2002
Copper for interconnects
Low-K for ILD
Low-K for ILD Applications
Interconnects
Copper a fast diffuser
Reluctance to introduce
newer materials
Damascene
Copper by Electroplating
As k reduces the mechanical strength is a problem
Low-K Porous Silica Films
K~2, for 45 nm node
Excellent mechanical strength
Japan, IEDM 2003
Porous SiOCH film (k=2.5), NEC, Japan
Metal Barriers & Cap Films
Copper interconnects require two types of barrier layers: a liner on the sides and a cap
on top of the damascene features. The key functions of the barrier layers are to prevent
copper and oxygen diffusion and promote adhesion with both the interlayer dielectric
(ILD) and the copper. The cap layer must also protect the copper from corrosion during
subsequent patterning steps and act as an etchstop for partially landed vias.
The current metal barrier technologies using a PVD Ta(N) liner and a PECVD Si(C)N
dielectric cap will be replaced within the next few years due to difficulties with
scaling these technologies to <100nm damascene feature sizes while maintaining
satisfactory performance for wire resistance and current density.
New liner technologies using ALD metal nitride alloys provide a one-generation delay
to the wire resistance problem but add new challenges for wire current density
scaling and integration with porous low-k ILD materials.
Novel Structures
Single Halo/Double Halo MOSFETs
Dynamic Threshold MOSFETs (DTMOS)
Electrically Induced Junction MOSFET
Double Gate & Gate All Around Structures
Silicon-on-Insulator/Silicon-on-Nothing Structures
Vertical MOSFETs
Strained Silicon Channels
Germanium Transistors
Hybrid substrates- (110) Silicon for p-MOS & (100) Silicon
for n-MOS integrated on the same substrates
Reduce Leakage and Power!
For the given I
off
, achieve maximum I
on
Source of Improvement Parameters affected Method
Charge density
1. S (inverse subthreshold slope)
2. Qinv at a fixed off-current
1. Double-gate FET.
2. Lowered operating temperature.
Carrier transport 1. Mobility (_eff)
2. Carrier velocity
3. Ballistic transport
1. Strained silicon.
2. High-mobility and -saturation-velocity
materials (e.g., Ge, InGaAs, InP).
3. Reduced mobility degradation factors (e.g.,
reduced transverse
electric field, reduced Coulomb scattering due
to dopants,
reduced phonon scattering).
4. Shorter channel length.
5. Lowered operating temperature.
Ensuring device
scalability to a
shorter channel
length
1. Generalized scale
length ().
2. Channel length (Lg)
1. Maintaining good electrostatic control of
channel potential
(e.g., double-gate FET, ground-plane FET, and
ultrathin-body SOI) by controlling the device
physical geometry and providing means to
terminate drain electric fields.
2. Sharp doping profiles, halo/pocket implants.
3. High gate capacitance (thin gate dielectrics,
metal gate
electrode) to provide strong gate control of
channel potential.
Parasitic resistance 1. R
ext
1. Extended/raised source/drain.
2. Low-barrier Schottky contact.
Parasitic capacitance 1. C
jn,
2. C
GD
, C
GS
, C
GB
1. SOI.
2. Double-gate FET.
New Device Structures
Looking for the Ideal MOSFET Structure
FinFET A 3-Dimensional Device
Advantages
Better control of SCE; High ON current,
Low OFF current
S~60mV/dec if Leff > 4Tsi+12Tox
Small DIBL if Leff > 2Tsi+12Tox
Fully depleted channel with possible intrinsic channel
Easy layout
FinFET is a variation of planar Double gate
MOSFET that has channels along vertical
direction
Existing challenges for
FINFET research
Experimental Studies:
V
T
engineering
Series resistance reduction
Demonstrate small gate length device with high performance (Low
over drive but high current)
Demonstrate the RF properties of the devices in circuits
Theoretical studies: Device parameter models including quantum effects
Compact model development
Geometrical channel width defined as
W=2*H
fin
+T
fin
Channel width can be increased by
Placing Number of fins in parallel
FinFET
Nowak, IBM
IBM
Finfet
2-D Modeling
Assumptions
Simple Gaussian S/D profiles & Uniformly doped Channel region
Uniformity in vertical Doping of S/D regions
Quantum Mechanical effects are not effective at 45nm node
Energy balance model considers Quantum effects
(in a potential well close to the surface) at 10nm node
Results
15% Under estimation in Drive Current
Variation of G
m
with fin width because of
parasitic resistance and charge centroid.
Necessary to solve coupled Poisson and Schrodinger
equations to find optimum G
m
At 10nm node
Mobility degradation (~10%) due to Quantum
effects
Drive current increases (~20%) due to ballistic
effects
Triple Gate Devices
Triple gate device shows 20% greater drive current than double gate
for same size
AMD proposed multi gate device and claims 50% greater drive than other
finFETs
Double gate FinFET
Triple get FinFET
Corner effects in FinFET
Corner device shows much improved subthreshold swing and DIBL over
Non corner device because of proximity effect
Finfet Design Considerations
Circuit Perceptive
Bench mark circuits like FO4, NAND pull stack,
and Pass gate mux are simulated using mixed
mode simulators
Larger & complex circuits cant be simulated
because of lack of good circuit models
Operational 6-transistor SRAM cell with cell size
of 4.8um
2
in 180nm technology by IBM
Conversion of existing SOI microprocessor design
to enable FinFET technology
(source: 1. E.J.Nowak, A Functional FinFET-DGCMOS SRAM Cell, IEDM 2002
2. T. Ludwig, FinFET Technology for Future Microprocessors, IEEE TED
Multiple gate replacement
Independent Double-Gate MOSFETs
Front and back (top or bottom) gates can operate independently
Better logic design
Dynamic V
T
control, and thus adaptive threshold
and leakage tuning.
Mixer Circuits for RF applications
M1 and M2 can be combined into one DGFET
Switch level model for conduction is controlled using signal A OR B
One of the advantages of planar double-gate devices over FinFETs from a
circuit designers perspective is the possibility of independent back-gate-bias.
Given the continued development of planar and quasi-planar double-gate
processes, circuit designers could find attractive uses for a hypothetical
device such as Ground-plane FinFET with independent bottom-gate control.
Fully Wrapped Contact >
End Contact > Top Contact
Contacting Finfets
UC Berkeley
T.J.King, UC Berkeley
Finfet S/D contact Design
Finfet Scaling
S/D Resistance
Elevated Source Drain
Silicides
Schottky Barrier MOSFETs (Metal source/drain)
Abrupt S/D Profiles
Gate resistance
- Novel gate architectures
- Metal gates
High-k integration with Finfets
- Fringing field effects
- Technology issues
Sorrounding gate - High-k dielectric - Metal gate- Schottky Barrier Strained
channel MOSFET ????
We need to use cylindrical coordinates to analyze the structure
Technology constraints
The Ideal MOS Transistor
Novel Device Operation
Esaki Tunnel FETs
Resonant Tunnel
Devices
Schottky Barrier
MOSFETs
Ballistic Transistors
Tunnel FET Operation 1
Tunnel FET Operation 2
K. Bhuwalka et. al. TED 2004
Alternative Device Structures
n substrate
+
n
n
+
+
p delta
+
intrinsic
intrinsic
Drain
Source
Isolation
Poly-gate
Gate
Oxide
Gate
+
+
+
n
n
p
Doping
i
i
0.0 0.5 1.0 1.5 2.0 2.5 3.0
0.0
5.0x10
-3
1.0x10
-2
1.5x10
-2
2.0x10
-2
2.5x10
-2
3.0x10
-2
3.5x10
-2
4.0x10
-2
VG=0V, 1V
VG=2V
VG=3V
VG=4V
VG=5V L=60 nm
I
D

(
A
)
VD (V)
0.0 0.2 0.4 0.6 0.8 1.0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
L =60nm, t
ox
=2.7nm
V
GS
=0-0.9V, step=0.1V
I
d
(
m
A
)
V
d
(Volts)
MOSFET Channel Engineering
Super steep retrograde wells
Halo implants
LAC MOSFETs
Channel Engineering Channel Engineering--Design Criteria Design Criteria
Maximization of Device Current Drive
(Current drive capability and
switching speed)
Minimization of device short channel
effects
Maximization of device punch through
resistance
Buried Oxide
Field
Oxide
Field
Oxide
Oxide
Spacer
Buried Oxide
Field
Oxide
Field
Oxide
TiSi2
Buried Oxide
Field
Oxide
Field
Oxide
Oxide
Spacer
S D
poly
Boron
Ge
S D
Amorphous Si
D S
poly
poly
(A)
(B)
(C)
Starting Material
SOI Wafers Si Film Thinning Down
Ge Implantation, 12, 20, and
40 Kev, 1 10
15
cm
-2
(35nm, 50nm, and 80nm)
Active Area Definition
and LOCOS
Threshold Voltage Adjustment
(For Conventional MOSFET)
Gate Oxidation (4 nm)
and Poly Deposition (200 nm)
E-beamPolyGate Lithography
and Poly Etch
Source/Drain Extension Implant
Large Angle Tilt Implant for V
TH
Adjustment (for LACMOSFET)
RTAAnneal (1020
o
C, 15seconds)
Oxide Spacer
Ti Deposition (20~35 nm)
Two Step RTASilicidation
Contact Hole
Metallization and FormingGas
A
B
C
LAC MOSFET Fabrication-Both Bulk and SOI Process
Development
UCLA & IIT Bombay
Approaching a Red Brick Wall
Technology Challenges
MOSFET Scaling Scenario
From H.S.P.Wong, Sub-100 nm CMOS, IEDM 1999 Short Course
Outline
Possible Solutions
Circuit approaches
The Gigascale Dilemma
1B T integration capacity will be available
But could be unusable due to power
Logic T growth will slow down
Transistor performance will be limited
Solutions
Low power design techniques
Improve design efficiency
Meet the performance specs by even higher
integration (of slower transistors)
Active power reduction techniques
Clock gating
Supply voltage reduction
Leakage power reduction techniques
Body biased transistors
Sleep transistors
Dual threshold voltage CMOS
Dual Vt techniques
MTCMOS sleep transistors
Domino logic techniques
Circuit Approaches
Dynamic Threshold MOSFETs
Low Voltage Operation
High Performance
Inter Device Isolation
Substrate Loading Effects
Layout Methodologies
Junction Leakage Currents
0.1 0.2 0.3 0.4 0.5 0.6 0.7
0
200000
400000
600000
800000
0.1 0.2 0.3 0.4 0.5 0.6 0.7
0
200000
400000
600000
800000
L=70 nm N-MOSFETs
t
ox
=1.5 nm
_____DTMOS
- - - - - Conventional
I
d
s
a
t

/

I
o
f f
Gate Voltage (V)
Technology Slowdown-Circuit Implications
Tox scaling will slow
downmay stop?
Vdd scaling will slow
downmay stop?
Vt scaling will slow
downmay stop?
Approaching constant
Vdd scaling
Energy/logic op will
not scale
0.1
10
10 3 1 0.35 0.13
V
d
d

(
V
o
l
t
s
)
Technology (m)
Million Tr
1.E-08
1.E-06
1.E-04
1.E-02
1.E+00
10 3 1 0.35 0.13
E
n
e
r
g
y
/
L
o
g
i
c

O
p
e
r
a
t
i
o
n

(
N
o
r
m
a
l
i
z
e
d
)
Technology (m)
Million Tr
Frequency & SD Leakage
0.9
1.0
1.1
1.2
1.3
1.4
0 5 10 15 20
Normalized Leakage (Isb)
N
o
r
m
a
l
i
z
e
d

F
r
e
q
u
e
n
c
y
0.18 micron
~1000
samples
20X
30%
Low Freq
Low Isb
High Freq
Medium Isb
High Freq
High Isb
S.Borkar
V
T
Distribution
0
20
40
60
80
100
120
-39.71 -25.27 -10.83 3.61 18.05 32.49
AVTn(mv)
#

o
f

C
h
i
p
s
~30mV
0.18 micron
~1000
samples
Low Freq
Low Isb
High Freq
Medium Isb
High Freq
High Isb
S.Borkar
Vdd & Temp Variation
4 0
5 0
6 0
7 0
8 0
9 0
1 0 0
1 1 0
T
e
m
p
e
r
a
t
u
r
e

(
C
)
0
50
100
150
200
250
H
e
a
t

F
l
u
x

(
W
/
c
m
2
)
Heat Flux (W/cm
2
)
Results in Vcc variation
Temperature Variation ( C)
Hot spots
Intel
Impact on Path Delays
Path Delay
Path delay variability due to variations in Vdd, Vt, and Temp
Impacts individual circuit performance and power
Optimize each circuit for full chip objectives Optimize each circuit for full chip objectives
Delay
P
r
o
b
a
b
i
l
i
t
y
Objective: full chip performance, power, and yield
Multivariable optimization of individual circuitVdd, Vt, size
Impact on Full Chip
Delay
Path Delay
P
r
o
b
a
b
i
l
i
t
y
Lower frequency, higher power Lower frequency, higher power
Due to variations in:
Vdd, Vt, and Temp
Delay Target
#

o
f

P
a
t
h
s
Deterministic
Leakage Power
F
r
e
q
u
e
n
c
yDeterministic
Probabilistic
10X variation
~50% total
power
Delay Target
#

o
f

P
a
t
h
s
Probabilistic
Leakage Control
Stack Effect Body Bias
Sleep Transistor
Vdd
Vbp
Vbn
-Ve
+Ve
Equal Loading Logic Block
2-10X reduction
2-1000X reduction
Circuit Design Tradeoffs
0
0.5
1
1.5
2
Low-Vt usage
low high
Higher probability of target frequency with: Higher probability of target frequency with:
1. 1. Larger transistor sizes Larger transistor sizes
2. 2. Higher Low Higher Low--Vt usage Vt usage
But with power penalty But with power penalty
0
0.5
1
1.5
2
Transistor
size
small large
power
target
frequency
probability
Outline
Possible Solutions
Circuit approaches
Shift in Design Paradigm
From deterministic design to probabilistic
and statistical design
A path delay estimate is probabilistic (not
deterministic)
Multi-variable design optimization for
Yield and bin splits
Parameter variations
Active and leakage power
Performance
Resistor
Network
4.5 mm
5
.
3

m
m
Multiple
subsites
PD & Counter
Resistor
Network
CUT
Bias
Amplifier
Delay
Die frequency: Min(F
1
..F
21
)
Die power: Sum(P
1
..P
21
)
Technology 150nm CMOS
Number of
subsites per die
21
Body bias range
0.5V FBB to
0.5V RBB
Bias resolution 32 mV
1.6 X 0.24 mm, 21 sites per die
150nm CMOS
Adaptive Body Bias--Experiment
Adaptive Body Bias
0%
20%
60%
100%
A
c
c
e
p
t
e
d

d
i
e
noBB
100% yield
ABB
Higher Frequency
N
u
m
b
e
r

o
f

d
i
e
s
Frequency
too
slow
f
target
too
leaky
f
target
ABB
FBB RBB
N
u
m
b
e
r

o
f

d
i
e
s
Frequency
too
slow
f
target
too
leaky
f
target
ABB
FBB RBB
97% highest bin
within die ABB
For given Freq and Power density For given Freq and Power density
100% yield with ABB 100% yield with ABB
97% highest freq bin with ABB for 97% highest freq bin with ABB for
within die variability within die variability
Active Power Reduction
Increase on-die Memory
Large on die memory provides:
1. Increased Data Bandwidth & Reduced Latency
2. Hence, higher performance for much lower power
Chip Multi Chip Multi--Processing Processing
SummaryDelaying Forever
Gigascale transistor integration capacity will be
availablePower and Energy are the barriers
Variations will be even more prominentshift from
Deterministic to Probabilistic design
Improve design efficiency
Multieverywhere, & SOC valued performance
Exploit integration capacity to deliver performance in
power/cost envelope
Fabrication-NMOSFET
Fabrication-NMOSFET (contd)
NMOS Inverter with Depletion Load
Inverter in IC form
Fabrication-NMOS inverter with depletion load
Birds beak, limitation in LOCOS
Isolation used for ULSI- Deep Trench
Inverter Fabrication (Contd)
(d)
Inverter Fabrication (Contd)

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GMRIT-Nanoelectronics

Dr. V. Ramgopal Rao

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