TESTING 4-BIT-ADDER BY COUNTER AND WALKING ONES

GROUP MEMBERS: DIEU-NHI LE (4-Bit-Adder) STEPHEN LAM (Shift Register) BAO DOAN (Counter) CHAU HOANG (Counter)

SPECIFICATIONS
Timing: Speed: Power: Shift Register Adder: P=20.1mW Counter Adder: P=20.5mW Total area: Shift Register Adder: A=0.13um^2 Counter Adder: A=0.076um^2

4-BIT-ADDER
- Testing 1-Bit, layout. - Testing 4-Bit, layout. - Verify the logic using Verilog.

1-BIT ADDER SCHE.

1-BIT ADDER LAYOUT

1-BIT ADDER EXTRACTED VIEW

1-BIT ADDER LVS

1-BIT-ADDER-TRANSIENT RESPONSE

1-BIT ADDER VERILOG

1-BIT ADDER TEST BENCH

4-BIT ADDER TEST BENCH

4-BIT ADDER LAYOUT

4-BIT ADDER EXTRACTED VIEW

4-BIT ADDER LVS

4-BIT ADDER TRANSIENT RESPONSE

4-BIT ADDER VERILOG

NAND3 SCHEMATIC

NAND3 LAYOUT

NAND3 EXTRACTED VIEW

NAND3 LVS

NAND3 TRANSIENT RESPONSE

NAND3 TEST BENCH

TRUTH TABLE FOR 7474 D FLIP-PLOP

Mode of operation Asynchronous set Asynchronous reset Prohibited Set Reset
0 = low 1 = high X = irrelevant = low to high transition of the clock pulse

Inputs Asynchronous Set 0 1 0 1 1

Outputs CLR 1 0 0 1 1 Synchronous CLK X X X D X X X 1 0 Q 1 0 1 1 0 QN 0 1 1 0 1

1 BIT D FLIP FLOP SCHEMATIC

1 BIT D FLIP FLOP LAYOUT

1 BIT D FLIP FLOP EXTRACTED VIEW

1 BIT D FLIP FLOP LVS

1 BIT D FLIP TRANSIENT RESPONSE

1 BIT D FLIP TEST BENCH

4-BIT BINARY COUNTER

A four bit binary counter we have designed in this project counts down and with every clock input moves up to the next higher state. It was designed using D type flip-flops. It has a SET signal which is setting when it is equal to 1.A CLEAR signal sets the counter back to 0.
0000 0001 0010 0011 0100 0101
0110

1111 1110

0111

1101

1100

1011

1010

1001

1000

COUNTER SCHEMATIC

COUNTER LAYOUT

COUNTER EXTRACTED VIEW

COUNTER LVS

COUNTER TRANSIENT RESPONSE

COUNTER TEST BENCH

COUNTER ADDER SCHEMATIC

COUNTER ADDER LAYOUT

COUNTER ADDER EXTRACTED VIEW

COUNTER ADDER LVS

COUNTER ADDER TRANSIENT RESPONSE

COUNTER ADDER TEST BENCH

4 BIT SHIFT REGISTER SCHEMATIC

4 BIT SHIFT REGISTER LAYOUT

4 BIT SHIFT REGISTER EXTRACTED VIEW

4 BIT SHIFT REGISTER LVS

4 BIT SHIFT REGISTER TRANSIENT RESPONSE

4 BIT SHIFT REGISTER TEST BENCH

4 BIT SHIFT REGISTER ADDER SCHEMATIC

4 BIT SHIFT REGISTER ADDER LAYOUT

4 BIT SHIFT REGISTER ADDER EXTRACTED VIEW

4 BIT SHIFT REGISTER ADDER LVS

4 BIT SHIFT REGISTER ADDER TRANSIENT RESPONSE

4 BIT SHIFT REGISTER ADDER TEST BENCH

4 BIT SHIFT REGISTER ADDER POWER

4 BIT SHIFT REGISTER ADDER POWER