Global Timing Constraints: PDF Created With Pdffactory Pro Trial Version

Global Timing Constraints
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Outline

Introduction Global Constraints The Constraints Editor Summary
Timing Constraints and Your Project

What effects do timing constraints have on your project? The implementation tools do not attempt to find the place & route that will obtain the best speed
Instead, the implementation tools try to meet your performance expectations Timing constraints improve the design performance by placing logic closer together so shorter routing resources can be used Note that when we discuss using the Constraints Editor, we are referring to the Xilinx Constraints Editor
Performance expectations are communicated with timing constraints
Without Timing Constraints
This design had no timing constraints or pin assignments
Note the logical structure of the placement and pins This design has a maximum system clock frequency of 50 MHz
With Timing Constraints
This is the same design with three global timing constraints entered with the Constraints Editor It has a maximum system clock frequency of 60 MHz Note that most of the logic is placed closer to the edge of the device, where the pins have been placed
More About Timing Constraints
Timing constraints should be used to define your performance objectives

Tight timing constraints will increase your compile time Unrealistic constraints will cause the implementation tools to stop Use the synthesis report or the Post-Map Static Timing Report to determine whether your constraints are realistic
After implementing, review the Post-Place & Route Static Timing Report to determine whether your performance objectives were met
If constraints were not met, use the Timing Report to determine the cause
Path End Points
Two types of path end points:

I/O pads Synchronous elements (flip-flops, latches, and RAMs) Step 1: Create groups of path end points Step 2: Specify a timing requirement between the groups All flip-flops, all I/O pads, etc.
Creating a timing constraint is a two-step process:

Global constraints use default groups of path end points
Skills Check
Review Questions

A single global constraint can cover multiple delay paths If the arrows are constrained paths, what are the path end points in this circuit? Do all of the registers have anything in common?
FLOP1 D Q FLOP2 D Q FLOP3 D Q
ADATA
CLK BUFG
OUT1
FLOP4 D Q
FLOP5 D Q
OUT2
BUS [7..0] = Combinatorial Logic
CDATA
Answers
What are the path end points in this circuit?
FLOP1, FLOP2, FLOP3, FLOP4, and FLOP5 They share a clock signal. A constraint that references this net could constrain all delay paths between all of the registers in the design
FLOP1 D Q FLOP2 D Q FLOP3 D Q
Do all of the registers have anything in common?
ADATA
CLK BUFG
OUT1
FLOP4 D Q
FLOP5 D Q
OUT2
BUS [7..0]
CDATA
Outline

The PERIOD Constraint
The PERIOD constraint covers paths between synchronous elements clocked by the reference net The PERIOD constraint does NOT cover paths from input pads to output pads (purely combinatorial), from input pads to synchronous elements, or from synchronous elements to output pads
ADATA
CLK BUFG
FLOP4 D Q FLOP5 D Q FLOP1 D Q FLOP2 D Q FLOP3 D Q
OUT1
OUT2
BUS [7..0]
CDATA
Features of the PERIOD Constraint
The PERIOD constraint uses the most accurate timing information so it can automatically account for:

Clock skew between the source and destination flip-flops Synchronous elements clocked on the negative edge Unequal clock duty cycles Clock input jitter
FF1
FF2
Assume:

CLK 50-percent duty signal on CLK BUFG INV PERIOD constraint of 10 ns Because FF2 will be clocked on the falling edge of CLK, the path between the two flip-flops will actually be constrained to 50% of 10 ns = 5 ns
Clock Input Jitter

Clock input jitter is one source of clock uncertainty Clock uncertainty is subtracted from:

PERIOD constraint setup paths OFFSET IN constraint setup paths PERIOD constraint hold paths OFFSET IN constraint hold paths OFFSET OUT constraint paths
Clock uncertainty is added to:

The Pad-to-Pad Constraint
Purely combinatorial delay paths do not contain any synchronous elements Purely combinatorial delay paths start and end at I/O pads and are often left unconstrained
Skills Check
Review Questions
Which paths are constrained by a PERIOD constraint on CLK1? Which paths are constrained by a pad-to-pad constraint?
FLOP D Q
PADA CLK1 PADB CLK2 BUFG PADC BUFG
LATCH D G Q
OUT1
RAM D
OUT2
Answers
Which paths are constrained by a PERIOD constraint on CLK1?
FLOP to LATCH PADC to OUT2

PADA
FLOP D Q LATCH D G Q
Which paths are constrained by a pad-to-pad constraint?
OUT1
CLK1 PADB CLK2 PADC BUFG BUFG

RAM D
OUT2
The OFFSET Constraint
The OFFSET constraints cover paths:

From input pads to synchronous elements (OFFSET IN) From synchronous elements to output pads (OFFSET OUT) OFFSET OUT
FLOP D Q FLOP D Q FLOP D Q
OFFSET IN
ADATA
CLK BUFG
FLOP D Q FLOP D Q
OUT1
OUT2
BUS [7..0]
CDATA
= Combinatorial Logic
Features of the OFFSET Constraint
The OFFSET constraint automatically accounts for the clock distribution delay

Provides the most accurate timing information Increases the amount of time for input signals to arrive at synchronous elements (clock and datapaths are in parallel) Reduces the amount of time for output signals to arrive at output pins (clock and datapaths are in series) Uses the jitter defined on the associated PERIOD constraint
The OFFSET constraint also accounts for clock input jitter
Clock Delay
Both the datapath delay and the clock distribution delay are used to calculate OFFSET constraints

OFFSET IN = T_data_In - T_clk_In OFFSET OUT = T_data_Out + T_clk_Out

T_data_In In T_clk_In T_data_Out Out
Clk OFFSET-IN
T_clk_Out OFFSET-OUT
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Skills Check
Review Question
Which paths are constrained by an OFFSET IN and an OFFSET OUT constraint in this circuit?
PADA
FLOP D Q
LATCH D G Q
CLK BUFG PADB

RAM
OUT1
OUT2 PADC
Answer
Which paths are constrained by an OFFSET IN and an OFFSET OUT constraint in this circuit?

OFFSET IN: PADA to FLOP and PADB to RAM OFFSET OUT: LATCH to OUT1, LATCH to OUT2, and RAM to OUT1
PADA
FLOP D Q LATCH D G Q
CLK BUFG PADB

RAM
OUT1
OUT2 PADC
Outline

Launching the Constraints Editor

In the Processes for Source window, expand User Constraints Double-click Create Timing Constraints
Entering PERIOD and Pad-To-Pad Constraints
The PERIOD and pad-topad constraints can be made on the Global tab Double-click here to make a PERIOD constraint Global pad-to-pad constraint Constraints can be deleted by selecting the constraint in the text window and pressing <Delete>
PERIOD Constraint Options

TIMESPEC name Specific constraint value

Active clock edge Duty-cycle Useful for designs with multiple clock signals Can define both frequency and phase relationships
Relative to another PERIOD constraint
Input jitter
Entering OFFSET Constraints
Global OFFSET IN/OUT constraints can also be made on the Global tab
Pad to setup = OFFSET IN
Clock to pad = OFFSET OUT
Outline

Review Question
Given the system diagram below, what values would you put in the Constraints Editor so that the system will run at 100 MHz?
Assume no clock skew between devices

Upstream Device Downstream Device 2 ns
3 ns
Answer
Given the system diagram below, what values would you put in the Constraints Editor so that the system will run at 100 MHz?
Upstream Device Downstream Device
7 ns
3 ns
10 ns
8 ns
2 ns
Answer: PERIOD = 10 ns , OFFSET IN = 7 ns and OFFSET OUT = 8 ns
Summary

Performance expectations are communicated with timing constraints The PERIOD constraint covers delay paths between synchronous elements The OFFSET constraint covers delay paths from input pins to synchronous elements and from synchronous elements to output pins The Constraints Editor allows you to create timing constraints
Where Can I Learn More?
Timing Presentation on the Web at http://support.xilinx.com
Documentation Technical Tips Timing & Constraints Getting Started The Timing Presentation
Timing Improvement Wizard on the Web at http://support.xilinx.com
Click the Problem Solvers menu

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Global Timing Constraints

PDF created with pdfFactory Pro trial version www.pdffactory.com

Introduction Global Constraints The Constraints Editor Summary

PDF created with pdfFactory Pro trial version www.pdffactory.com

Timing Constraints and Your Project

Performance expectations are communicated with timing constraints

PDF created with pdfFactory Pro trial version www.pdffactory.com

Without Timing Constraints

This design had no timing constraints or pin assignments

PDF created with pdfFactory Pro trial version www.pdffactory.com

With Timing Constraints

PDF created with pdfFactory Pro trial version www.pdffactory.com

More About Timing Constraints

Timing constraints should be used to define your performance objectives

PDF created with pdfFactory Pro trial version www.pdffactory.com

Path End Points

Two types of path end points:

Creating a timing constraint is a two-step process:

Global constraints use default groups of path end points

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BUS [7..0] = Combinatorial Logic

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What are the path end points in this circuit?

Do all of the registers have anything in common?

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Introduction Global Constraints The Constraints Editor Summary

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The PERIOD Constraint

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Features of the PERIOD Constraint

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Clock Input Jitter

Clock uncertainty is added to:

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The Pad-to-Pad Constraint

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PADA CLK1 PADB CLK2 BUFG PADC BUFG

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Which paths are constrained by a PERIOD constraint on CLK1?

FLOP to LATCH PADC to OUT2

Which paths are constrained by a pad-to-pad constraint?

CLK1 PADB CLK2 PADC BUFG BUFG

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The OFFSET Constraint

The OFFSET constraints cover paths:

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Features of the OFFSET Constraint

The OFFSET constraint also accounts for clock input jitter

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OFFSET IN = T_data_In - T_clk_In OFFSET OUT = T_data_Out + T_clk_Out

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CLK BUFG PADB

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CLK BUFG PADB

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Introduction Global Constraints The Constraints Editor Summary

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Launching the Constraints Editor

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Entering PERIOD and Pad-To-Pad Constraints