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    The document discusses the design process for VLSI integrated circuits using Verilog HDL. It describes the typical steps as defining specifications, behavior modeling, register-transfer level (RTL) modeling, functional verification, logic synthesis, gate-level netlisting, logic verification, floorplanning, placement, routing, layout verification, and fabrication. It highlights the importance of Verilog HDL in allowing design at a very abstract level without choosing a fabrication technology, and how logic synthesis tools can automatically convert the design to any target technology.

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    The document discusses the design process for VLSI integrated circuits using Verilog HDL. It describes the typical steps as defining specifications, behavior modeling, register-transfer level (RTL) modeling, functional verification, logic synthesis, gate-level netlisting, logic verification, floorplanning, placement, routing, layout verification, and fabrication. It highlights the importance of Verilog HDL in allowing design at a very abstract level without choosing a fabrication technology, and how logic synthesis tools can automatically convert the design to any target technology.

    Copyright:

    Attribution Non-Commercial (BY-NC)
    Download as PPT, PDF, TXT or read online from Scribd
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    14 views10 pages

    Bai 1 Tong Quan

    Uploaded by

    orphanheart
    The document discusses the design process for VLSI integrated circuits using Verilog HDL. It describes the typical steps as defining specifications, behavior modeling, register-transfer level (RTL) modeling, functional verification, logic synthesis, gate-level netlisting, logic verification, floorplanning, placement, routing, layout verification, and fabrication. It highlights the importance of Verilog HDL in allowing design at a very abstract level without choosing a fabrication technology, and how logic synthesis tools can automatically convert the design to any target technology.

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    Attribution Non-Commercial (BY-NC)
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    of 10

    Baøi 1: Toång quan

    Thieát keá soá vôùi Verilog HDL


    Löu ñoà thieát keá VLSI IC ñieån hình

    Böôùc 1: Ñaëc taû thieát keá.


    Böôùc 2: Moâ taû haønh vi.
    Böôùc 3: Moâ taû RTL (HDL)
    Böôùc 4: Kieåm tra vaø xaùc minh
    chöùc naêng.
    (khoâng ñaït: böôùc 3)
    Böôùc 5: Toång hôïp logic.
    Böôùc 6: Netlist möùc coång.
    Böôùc 7: Kieåm tra vaø xaùc minh
    logic.
    Löu ñoà thieát keá ñieån hình VLSI IC
    (tieáp theo)

    Böôùc 8: Laäp sô ñoà taàng, ñònh vò


    trí, ñònh tuyeán.
    Böùôùc 9: Layout vaät lyù.
    Böôùc 10: Xaùc minh layout.
    (khoâng ñaït: böôùc 8, böôùc
    3)
    Böôùc 11: Thöïc hieän.

    Chöõ bình thöôøng: möùc bieåu dieãn


    Ñaëc taû: ñöôïc vieát tröôùc tieân,
    moâ taû moät caùch tröøu töôïng
    chöùc naêng, giao dieän vaø caáu
    truùc toång theå cuûa maïch soá
    caàn thieát keá. Ngöôøi laäp kieán
    truùc khoâng caàn nghó veà caùch
    thöùc thöïc hieän maïch soá.
    Moâ taû haønh vi: ñöôïc taïo ra ñeå
    phaân tích thieát keá döïa vaøo
    chöùc naêng, hieäu suaát, tuaân
    theo caùc chuaån vaø caùc vaán ñeà
    möùc cao. Moâ taû haønh vi coù theå
    ñöôïc vieát baèng HDL. Moâ taû
    haønh vi ñöôïc bieán ñoåi thuû coâng
    Coâng cuï toång hôïp logic seõ
    bieán ñoåi moâ taû RTL thaønh
    netlist möùc coång. Netlist möùc
    coång laø moâ taû maïch soá döïa
    vaøo caùc coång vaø keát noái giöõa
    chuùng.
    Netlist möùc coång laø ñaàu vaøo
    cuûa coâng cuï laäp sô ñoà taàng,
    ñònh vò trí vaø ñònh tuyeán, coâng
    cuï naøy seõ taïo ra layout.
    Layout ñöôïc kieåm tra vaø keá ñeán
    ñöôïc cheá taïo treân chip.
    Nhö vaäy, hoaït ñoäng thieát keá soá
    Coâng cuï toång hôïp haønh vi
    ñöôïc ñöa vaøo, taïo ra moâ taû RTL
    töø moâ taû haønh vi hoaëc giaûi
    thuaät  vieäc thieát keá maïch soá
    töông töï nhö laäp trình maùy tính
    möùc cao.
    Ngöôøi thieát keá trôû thaønh ngöôøi
    ñieàu khieån caùch thöùc maø coâng
    cuï töï ñoäng thieát keá seõ thöïc
    hieän  ngöôøi thieát keá caàn
    hieåu bieát veà nhöõng khía caïnh
    cuûa heä phöông phaùp thieát keá,
    söû duïng coâng cuï thieát keá ñeå
    Taàm quan troïng cuûa Verilog HDL

    Thieát keá coù theå ñöôïc moâ taû


    ôû möùc raát tröøu töôïng baèng
    caùch söû duïng HDL. Ngöôøi thieát
    keá coù theå vieát moâ taû RTL maø
    khoâng caàn choïn löïa coâng ngheä
    cheá taïo cuï theå.
    Caùc coâng cuï toång hôïp logic coù
    theå töï ñoäng chuyeån ñoåi thieát
    keá ñeán coâng ngheä cheá taïo
    baát kyø.
    Taàm quan troïng cuûa Verilog HDL
    (tieáp theo)
    Neáu moät coâng ngheä môùi noåi
    leân, ngöôøi thieát keá khoâng caàn
    thieát keá laïi maïch maø chæ ñôn
    thuaàn nhaäp moâ taû RTL vaøo
    coâng cuï toång hôïp vaø taïo ra
    netlist möùc coång môùi, söû duïng
    coâng ngheä cheá taïo môùi.
    Coâng cuï toång hôïp logic seõ toái
    öu hoùa maïch theo dieän tích vaø
    ñònh thôøi ñoái vôùi coâng ngheä
    Xu höôùng noåi baät

    Moät xu höôùng ñang noåi baät ñoái


    vôùi vieäc thieát keá möùc heä
    thoáng laø heä phöông phaùp troän
    laãn treân-xuoáng vaø döôùi leân,
    trong ñoù ngöôøi thieát keá söû
    duïng caùc module Verilog coù saün,
    caùc khoái cô baûn xaây döïng saün
    hoaëc caùc khoái loõi cuûa nhaø
    cung caáp ñeå nhanh choùng ñöa ra
    moâ phoûng heä thoáng. Chi phí
    Xu höôùng noåi baät (tieáp theo)

    Thí duï, ta khaûo saùt moät heä


    thoáng coù CPU, chip ñoà hoïa, bus
    heä thoáng. Ngöôøi thieát keá CPU
    muoán xaây döïng CPU theá heä keá
    tieáp ôû möùc RTL, nhöng laïi muoán
    söû duïng moâ hình haønh vi cho
    chip ñoà hoïa & chip I/O vaø mua
    moâ hình bus heä thoáng cuûa nhaø
    cung caáp. Nhö vaäy, vieäc moâ
    phoûng ôû möùc heä thoáng ñoái
    vôùi CPU coù theå hoaøn thaønh vaø
    hoaït ñoäng raát nhanh tröôùc khi

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