VERILOG CODE FOR MAC UNIT:

module MAC_UNIT(clk,rst, a,b, z);

input clk,rst;
input [2:0] a,b;
output [5:0] z;
wire [5:0] w;
multiplier U1(.a(a),.b(b),.p(w));
pipo U2(.RIN(w), .clk(clk),.rst(rst),.ROUT(z));
endmodule
VERILOG CODE FOR MULTIPLIER:
module multiplier(a,b, p);
input [2:0] a,b;
output [5:0] p;
wire [7:0]u;
wire [1:0]su;
wire [8:0]i;
and (p[0],a[0],b[0]);
and (u[0],a[1],b[0]);
and (u[1],a[2],b[0]);
and (u[2],a[0],b[1]);
and (u[3],a[1],b[1]);
and (u[4],a[2],b[1]);
and (u[5],a[0],b[2]);
and (u[6],a[1],b[2]);
and (u[7],a[2],b[2]);
hadd h1(.l(u[0]),.m(u[2]),.sum(p[1]),.cry(i[0]));
hadd h2(.l(i[0]),.m(u[1]),.sum(su[0]),.cry(i[1]));
hadd h3(.l(u[3]),.m(u[5]),.sum(su[1]),.cry(i[2]));

hadd h4(.l(su[0]),.m(su[1]),.sum(p[2]),.cry(i[4]));
hadd h5(.l(i[1]),.m(i[2]),.sum(i[5]),.cry(i[6]));
or (i[7],i[5],i[4]);
fadd f3(.d(i[7]),.e(u[4]),.cin(u[6]),.s(p[3]),.cout(i[8]));
fadd f4(.d(i[8]),.e(i[6]),.cin(u[7]),.s(p[4]),.cout(p[5]));
endmodule
VERILOG CODE FOR PARALLEL IN PARALLEL OUT:
module pipo(RIN, clk,rst, ROUT);
input [5:0] RIN;
input clk,rst;
output [5:0] ROUT;
reg [5:0] ROUT;
always @(posedge clk or negedge rst)
begin
if(!rst)
begin
ROUT <= 6'b000000;
end
else
begin
ROUT <= RIN;
end
end
endmodule
VERILOG CODE FOR FULL ADDER:
module fadd(s,cout,d,e,cin);
input d,e,cin;

output s,cout;
assign s = (d ^ e ^ cin);
assign cout = ((d&e) | (e&cin) | (d&cin));
endmodule

VERILOG CODE FOR HALF ADDER:

module hadd(sum,cry,l,m);
input l,m;
output sum,cry;
wire sum,cry;
assign sum = (l^m);
assign cry = (l&m);
endmodule

FIG 4.2 SCHEMATIC VIEW OF MAC UNIT

FIG 4.3 WAVEFORM FOR MAC UNIT