EWSD Coordination Processor (CP)

1 Functional Description

1.1 Introduction

The EWSD system consists of number of largely autonomous

subsystems. The subsystems each have their own microprocessor controls, for
example the controls for the digital line units is DLUC and for the LTG is the
groups processor (GP). The distributed microprocessor controls and the data
transfer between them are coordinated by the coordination processor (CP).
Figure on the next page shows the position of the CP in the EWSD Classic and
EWSD powernode configurations..

The Coordination Processor is the heart of a Siemens exchange. It

controls all other functional units, does the main call processing tasks and
processes MML.
The CP is divided into several subunits:

• Two base processors (BAP) for maintenance and call processing tasks
• up to 6 call processors (CAP) for call processing only in case of EWSD Classic
or
up to 10 call processors (CAP) for call processing only in case of EWSD
Powermode
• up to 4 input/output controllers as interfaces to input/output processors in case
of EWSD Classic or
up to 2 input/output controllers as interfaces to input/output processors in case
of EWSD Powermode
• two ATM bridge processors (AMP) for connection of the SSNC with EWSD
Powernode
• a duplicated common memory (CMY)
• a duplicated bus system (BCMY) between the BAP, CAP, IOC, AMP and CMY
• several input/output processors for connecting external equipment

The CP performs the following functions in a network node:

Call processing
• digit translation
• routing
• zoning
• path selection through the switching network
• call charge registration
• traffic data administration

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EWSD Coordination Processor (CP)
• network administration

LTG
DLU
LTG

LTG

SN
CCNC

SYP
MB
MTD &
MDD
CP
OMT CCG

Position of the CP113 in EWSD Classic

LTG
DLU
LTG

LTG

MDD SN
SSNC
MOD

MB
MTD &
MDD
CP
OMT CCG

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EWSD Coordination Processor (CP)

Operation and maintenance

• input and output from/to external memories (EM)

• communication with the local operation and maintenance terminals (NetM boot or
BCT Boot/ OMT) via V.24
• communication with the Net M either via X.25 (EWSD Classic) or Via
SSNC/Ethernet (EWSD Powernode)

Safeguarding

• self -supervision
• error detection
• error handling

The coordination processor 113 (CP113) is supplied for all sizes of switch-
ing center. The CP113 is a multiprocessor which can be expanded progressively
( by adding call processors). It satisfies all safeguarding and performance
requirements exceptionally well.

The CP area also includes the system panel ( SYP). The SYP indicates alarms
(audio & visual) and advisories from system-internal and system-external
supervisory units.

Other important functions in the CP area are handled by :

- message buffer (MB),

- central clock generator (CCG).

1.2 Hardware

The CP113 consists of a modular multiprocessor system with a processing

width of 32 bits and an addressing capacity of 4 Gbytes. The CP113 C
comprises the following hardware functional units:

• base processors (BAP)

• call processors (CAP); not included in the basic capacity stage
• ATM bridge processors (AMP) ; in case of EWSD powernode
• input/output controls (IOC)

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 EWSD Coordination Processor (CP)
• bus for common memory (BCMY)
• common memory (CMY)
• input/output processors (IOP):

Maximum configuration of
CP113C

Basic configuration 11 IOP IOP IOP IOP

. 11
of CP 113C,
. .
.
0
IOP IOP 0 IOP IOP

B:IOC B:IOC

CAP5 IOC3
CAP0 AMP0 AMP1 BAPM BAPS IOC0 IOC1 IOC2

BCMY1

BCMY0

CMY1

CMY0

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EWSD Coordination Processor (CP)

a) IOP:MB (input/output processor for message buffer)

b) IOP:TA (input / output processor for time and alarms)

c) IOP:LAU (input/output processor for X.25 line adaption unit)

d) IOP:UNI (input/output processor unified for O & M devices)

There are two BAP in the CP113, one is called the master, performing all the
maintenance tasks and, if necessary, call processing, the other one is called spare,
which does only call processing. The master/spare status of the BAP can be
changed either manually with the MML command COM BAP; or automatically by
the system itself. This automatic change is normally done once a day. If a BAP
Master fails, its functions are handled by the spare BAP which is also automatically
configured to the status of master.

TIP

The optional call processors can not replace the functionality of the BAP.

The basic configuration of the CP113C can be expanded as necessary by adding

similar functional units. This is true for computing and memory capacity, and also
for the connection of call processing plus operation and maintenance peripherals.
The current expansion options are shown in table on next page.

The operation and maintenance periphery (O&M periphery) and data

communication periphery can be expanded as required for the CP113C. The
following devices can be attached:

• magnetic tape device (MTD)

• magnetic disk device (MDD)
• magneto-optical disk device(MOD)
• operation and maintenance terminal ( NetM boot or BCT Boot/ OMT)
• data links to data communication devices or to data terminal equipment with V.24,
V.35, V.36 interfaces and with the BX.25/X.25 protocol

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EWSD Coordination Processor (CP)
• maintenance panel (used only by TAC staff for special fault clearance procedures).

Unit Minimum Maximum

BAP 2 2
CAP 0 6 (Classic)
10 (Powernode)
IOC 2 4 (Classic)
2 (Powernode)
AMP 0 2 (only is Powernode)
CMY(Mbytes) 64 1024
B:CMY 2 2
IOP:MB 8 (Classic) 14
4 (Powenode)
IOP:TA 2 2
IOP:UNI 2 8
IOP:SCDP(IOP:LAU) 0 12

Minimum and Maximum Configuration of CP 113 C

The call processors (CAP) deal only with call processing functions. They
form a redundant pool together with the BAPS. Even if one processor fails (either a
BAP or a CAP), the CP113 can thus still provide the full nominal load (n + 1
redundancy). There is no CAP in the basic capacity stage.
The two buses to the common memory (BCMY0, BCMY1) transfer and
save identical information during normal operation. If a fault occurs in one of the
functional units, it is disconnected from the trouble-free units.
The CP113 has a 2-level memory concept. This is one of the main reasons
for its high switching performance. A separate local memory (LMY) is available to
each processor, in addition to the common memory (CMY). Distributing the data
and programs between processor-specific memories and a common memory for all
processors results in short access times. The local processor memories contain the
dynamically relevant programs and the data which is only required by their own
processors. The common memory contains all the common data, as well as
programs and data which are not required very often.

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 EWSD Coordination Processor (CP)
The common memory also handles data exchanges between the processors.
The stored data is supervised in the CMY and the LMYs on the basis of a check
code. This code enables 1-bit errors to be corrected automatically and all 2 bit
errors to be detected, and with a high probability it also enables greater bit
mutilations to be detected.

The input/output controls (IOC) coordinate and supervise accessing of the

CMY by the input/output processors (IOP). The connection between each IOC and
its associated IOPs is set up by a separate bus system per IOC for input/output
control (B:IOC). Up to 12 IOPs can be connected to a B:IOC.

The IOCs and the IOPs have been designed so that they can assume respon-
sibility for the functions of the partner units if these fail. The redundant O&M data
equipment (O&M periphery) is always connected to different IOCs. If one IOC or
the corresponding input/output processors fail, all inputs and outputs are diverted
via the partner IOC.( to or from the redundant O&M and data equipment).

1.2.1 BAP, CAP and IOC

The base processors, call processors and input/output controls are built using identical
hardware components and can therefore be described together.

Each processor comprises the following:

• two processing units (PU)

• a local memory (LMY)
• a common interface (CI)
• an interface to the bus system for input/output control (BIOC)

The interface to the BIOC is part of the CI and thus physically present in all
processors. However, it is only activated when used as an IOC.

Processing Unit

The processing unit (PU) is duplicated. Mutual checking by the two Pus allows fast
error detection and handling, thus preventing the effects of errors from spreading. The
PU0 is always the master unit in normal operation. During write cycles to the
memories, the data are always sent by the master PU, while in read cycles both PUs
receive the data. The core of the processing unit is a microprocessor. The programs of

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EWSD Coordination Processor (CP)
the system-specific software and function-oriented user software run on this
microprocessor.

Local Memory

Dynamically important programs and data only required by a particular processor are
stored in the local memory (LMY) of the processor. This memory can only be
addressed by the processor itself or, in the IOC, also by the IOP.

In addition to the local memory, a flash EPROM is also available. It includes the
firmware for the hardware recovery, the loader, the diagnosis programs and also the
IOC firmware.

Common Interface

The processor is connected to both buses of the common memory (BCMY) by means
of the common interface (CI). All accesses to the common memory (CMY) and the
inter processor communication are performed via this interface. It is also possible to
connect a maintenance panel for system checks and special fault clearance to the
common interface.

Interface to the Bus System for Input/Output Control

The interface to the bus system for input/output control (BIOC) is only active when
the processor is used as an input/output control (IOC). The interface is part of the
common interface. The interface to the BIOC connects the local bus of the IOC with
the bus system for input/output control. A maximum of 12 input/output processors
(IOP) can be connected to the BIOC.

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EWSD Coordination Processor (CP)

BIOC PEX

Interface to BIOC (part of CI; only active in IOC)

Processing unit 0 Processing unit 1

(PU0) (PU1)

Local Memory
(LMY)

Common interface (CI)

Maintenance Partner
panel BAP

BCMY0

BCMY1

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Structure of BAP, CAPS and IOC
 EWSD Coordination Processor (CP)

1.2.2 ATM Bridge Processor (AMP)

The ATM Bridge processor (AMP) is the interface between the ATM equipment in the
SSNC and the coordination processor CP113C. Its task is to convert the ATM oriented
data streams from SSNC to the internal EWSD format. AMP messages being
transferred between SSNC and CP are:

• SS7 messages relevant for the CP

• Internal OAM- messages as e.g. Load Control, checking of data consistency
The AMP is connected in the CP113 C (on the EWSD side), like the other processors
(BAP, CAP, IOC) at the common memory bus (B:CMY).

The AMP is operated in accordance with the redundancy principle of all CP

components on a pair basis. An AMP pair works in the working/ spare mode, i.e. both
AMPs receive the same messages in parallel, but the active one only transmits the
messages. The spare buffers all messages, but does not access the CMY. In the event of
a soft switchover, if necessary, it takes over full operation, whereby it resumes without
losing any message.

In addition to the AMP function (on the CP side), the AMP module also contains the
ATM bridge function (on the SSNC side), which implements the functional partition
between the EWSD and the SSNC.

• There exists a duplicated bridge between CP (AMP) and SSNC (AMX of ASN).
• Each physical bridge is a 207 Mbit/s optical fiber connection between one AMP
and the duplicated AMX (side 0 and side 1 of AMXE):

- bridge 0 is the connection between AMP0 and side 0 & 1 of AMXE

- bridge 1 is the connection between AMP1 and side 0 & 1 of AMXE

• Either bridge 0 or bridge 1 is active, the other is stand by. The ATM cells are
transmitted via the active bridge to both AMX multiplexers. On the receive
side, the AMP (ATM230) of the active bridge works in accordance with the
redundancy path combining method, i.e. the first fault-free incoming ATM cell
is accepted, the subsequent incoming ATM cells is discarded.

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EWSD Coordination Processor (CP)
• The AMP/ AMX connection is implemented as a fiber optical connection.
Optical fibers are converted into an electrical connection by an adapter which
is inserted in the corresponding cable plug-in position at the mounting locations
of the AMX. This adapter FOTX (fiber optical transceiver, type E) is fixed in
the cable plug-in positions and can only be removed using a special extraction
tool.

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EWSD Coordination Processor (CP)

CP113C
ASN

AMPC- 0
FOTX FOTX ATM230
Checker
AMXE
Side 0 FOTX FOTX
ATM230
Master

AMPC- 1

FOTX FOTX ATM230

Checker
AMXE
Side 1
FOTX FOTX ATM230
Master

AMP Functional Structure and Interfaces

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 EWSD Coordination Processor (CP)

1.2.3 Bus for Common Memory (BCMY)

The bus for common memory (BCMY) connects all processors (BAP, CAP), including
the input/output controls (IOC), with each other and with the common memory
(CMY). Data and address for read and write cycles in the CMY are transferred, and
the inter-processor communication (IPC) is handled via the BCMY. The BCMY is
duplicated for safety reasons. The two BCMY operate synchronously and process
identical information. In certain cases the two BCMY can work independently of each
other (for example, for test purposes).

A BCMY consists mainly of the following function blocks:

• processor interface units (PI),

• BCMY arbiter,
• memory interface,
• bus clock generator,

In the basic configuration of the CP113, the BCMY has one processor interface
group (PI group 0) with 4 processor interfaces PI0.....PI3. To expand this, further
processor interface groups (PI1......PI3), each with 4 processor interfaces, can be
added.

Processor Interface Unit

There is one processor interface unit (PI) each for the processors (BAP, CAP, AMP
and IOC). It connects the BCMY with the processor. The PI sends the addresses
and data transferred by the processor or IOC to the BCMY at the correct time and
passes data received via the BCMY to the processor or IOC. In the minimal
configuration of the CP113, the BCMY has one processor interface group (PI
group 0) with 4 processor interfaces PI0… PI3. To expand this, further processor
interface groups (PI1… PI3), each with 4 processor interfaces, can be added.
Processor interface group 3 is used for the CAP 6 to 9 which are only used in
EWSD powenode. Therefore, PI group 3 is never installed in EWSD classic.

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 EWSD Coordination Processor (CP)

CAP0 ……………….. CAP5 CAP6 CAP7

IOC2/3 or AMP0/1 CAP2 CAP8 CAP9
BAP0 IOC0 BAP1 IOC1 PIA

PI0 PI3

BCMY PI group3
Arbiter
PI group1 PI group2

PI group0

PI groups 1 to 3

BCMY Arbiters of
Operation and
memory Bus clock PI groups 1 to 3
maintenance
interface generator
control Only used with
EWSD Powernode
BCM MTI

PIA
Maintenance
Panel CMY0 CMY1

Extension of CP113C

PIA Processor interface arbiter

BCM Bus clock generator maintenance control
MTI Memory and tracer interface

Structure of the bus for common memory (BCMY)

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EWSD Coordination Processor (CP)
BCMY Arbiter

The BCMY arbiter controls the data flow between the functional units connected to
the BCMY. On request, the BCMY arbiter assigns the bus for access to a memory
bank from the processors one time slot at a time. Functionally, the BCMY arbiter is
structured into a processor selection circuit and a group selection circuit. The
processor selection circuit controls bus assignments within the processor interface
group (PI group). The group selection circuit controls the group selection if more than
one PI group is available.

Memory Interface

The memory interface is the link between the BCMY and the two common memories
(CMY0, CMY1). When writing, the data and address are simultaneously transferred
via both BCMY to the two common memories, A variable setting defines which CMY
(CMY0 or CMY1) accepts the data and address from which BCMY (BCMY0 or
BCMY1). Likewise, when reading, each BCMY receives the read data from the CMY
assigned to it and transfers the data to the requesting processor in the correct time
slot. The processor only accepts the read data from one BCMY. The selection of the
BCMY from which the processor accepts the data is made by a preferred direction
that can be set in the processor by the software. If an error occurs, the preferred
direction can also be switched over immediately by the hardware.

Bus Clock Generator

In normal operation the clock system of the BCMY0 supplies timing signals. The
timing signals are transferred internally to the other BCMY, to all processors and to
the CMY.

The processors operate asynchronously to the BCMY. They use the BCMY clock for
synchronization when transmitting and receiving data on the BCMY. CMY0 and
CMY1 receive the bus clock by means of individual clock lines, each of which can be
switched independently of the clock line to the other CMY (for failure protection). The
CMY operates in synchrony with the BCMY, using the BCMY clock. The CMY clock
system is only used for CMY-internal processes if no BCMY clock is available.

Operation and Maintenance Control

Operation and maintenance control is responsible for maintenance and safeguarding

functions. For example, it initiates test and diagnosis hardware within the BCMY and
analyzes hardware states. Operation and maintenance control also constitutes the
interface for connecting the maintenance panel to the BCMY.

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 EWSD Coordination Processor (CP)

1.2.4 Common Memory (CMY)

The common memory (CMY) includes among other things, the common database for
all processors, the input and output lists for the IOP:MB and the communication areas
for the IOP to the O & M periphery. The CMY is duplicated in order to ensure a high
level of availability. The two CMY (CMY0, CMY1) can be accessed by all processors
and input/output controls as well as by the IOP via the two buses to the common
memory (BCMY0, BCMY1). In normal operation, both CMY perform all write and
read cycles in synchronous cycles. However, it is also possible to operate both CMY
independently of one another (splitting mode).

The CMY consists of the memory control and the storage medium.

1.2.5 Input/Output Processors (IOP)

Different types of input/output processors (IOP) connect the CP113C/CR with the
other units in the network node, the external memories, the operation and
maintenance terminal or basic craft terminal, the operation and maintenance center
(OMC), via data lines) and computer centers (also via data lines). Fig. on next page
shows the structure of the input/output system of the CP113C with two input/output
controls (IOC).

Table on page-6 lists the minimum and maximum numbers of IOP types that can be
connected. If more than one IOP of the same type is used, they must be connected to
different IOCs to improve safeguarding.

Apart from the microprocessor, the main components of the IOPs are the EPROM and
RAM, the timers, the interrupt handlers, the interface to the B:IOC and one or more
interfaces to the peripheral units.

The IOPs are initialized by the BAPM. The control programs of the IOP: LAU and
IOP: UNI are reloaded from the CMY. The control programs of all the other IOPs are
stored in the EPROM. The BAPM issues commands to the IOPs, which process and
execute them autonomously.

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EWSD Coordination Processor (CP)

Input/output Processor for Message Buffer

The input/output processors for the message buffer (IOP:MB) are the CP113C
interfaces to the functional units in the network node. All subsystems and functional
units are supplied via two IOP:MB for reasons of operational reliability. If one of the
two IOP:MB fails, the remaining processor takes over the data exchange functions by
itself. The following units are connected to the IOP:MB:

• the message buffer groups (MBG),

• the central clock generators (CCG),
• the common channel signaling network control (CCNC, only with EWSD Classic)
and
• the system panel (SYP, only with EWSD Classic).

Instead of the SYPC the Profi Bus may be used. This case requires the specific HW type
IOP:MB/PB (PB=Profit Bus). This variant may also be employed for the other places of
IOP:MB. It is possible to mix the normal IOP:MB and IOP:MB/PB.

The number of IOP:MB used depends on the size of the switching network. For each pair of
message buffer groups (SN0, SN1), two IOP:MB are necessary.

Input/output Processor for Time and Alarms

The input/output processor for time and alarms (IOP:TA) contains the hardware clock
of the CP113C and interfaces for accepting external alarms. The duplicated hardware
clock of the IOP:TA is synchronized by a clock supplied by the central clock generator
(CCG). The hardware clock generates the date as well as the time in hours, minutes
and seconds. The time is displayed on the front panel of the module.

Alarms occur in racks of the CP area which cannot be assigned to specific functional
units, e.g. fan alarms. The IOP:TA accepts these alarms and reports them to the
safeguarding software in the BAP. The IOP:TA has alarms interfaces to a maximum of
5 racks.

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 EWSD Coordination Processor (CP)

BIOC0
IOP:UNI
IOP:MB
CCNP MDD
IOP:PMB BIOC1
MOD
Number depends
IOP:MB on SN size. MTD
MBG OMT/BCT/
IOP:MB

NETM boot
IOP:MB
Data Lines
CCG IOP:MB IOP:UN1
MDD
MOD
IOP:TA
Alarm function
: monitors fans MTD
of CP racks
IOP:TA
OMT/BCT/

IOP:MB NETM boot

SYPC Data Lines
IOP:MB
IOP:SCDP
Profibus

SYPC or Alarm
Profi bus Input IOP:MB/PB

LCUB LAUB
Alarm
X.25 links to e.g.
Output (IOP:LAU) (LAU)
OMC, CT or billing
center normally with
IOP:MB/PB EWSD Classic
CT LCUB LAUB

(IOP:LAU) (LAU)

IOC0
IOC1

BCMY0

BCMY1

Structure of the CP 113C input/output system

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 EWSD Coordination Processor (CP)
Input /Output Processor Unified for O & M Devices

The following devices or lines can be connected via the input/output processor unified for O
& M devices (IOP:UNI):
• magnetic tape device (MTD),
• magneto-optical disk unit (MOD)
• magnetic disk device (MDD),

and optionally:

• one O & M terminal (OMT or BCTboot or NetM boot) and 2 data lines or 3 data lines,

The magneto-optical disk unit is used as a storage medium instead of or in addition to the
magnetic tape, to improve the operating activities, particularly to reduce the start up and
backup times. The MOD can be connected on the same SCSI bus as the MTD and MDD. At
the interface to the CP, the MOD is driven like an MTD. The maximum number of
MOD/MTD which can be connected is 2 per IOP:UNI.

Three connections are provided for OMT or BCT boot or NetM boot and data lines. One
OMT/BCT/NetM and 2 data lines, or alternatively 3 data lines, can be connected to them
directly or via a Modem.

Input/Output Processor for Line Adaption Unit

The input/output processor for line adaption unit (IOP:LAU) is used for connecting X.25-
equipment to the exchange, such as OMC or craft terminal. It consists of just a single
module, the line control unit module B, LCUB. The line adaption unit module B (module
LAUB) is used for connecting the IOP:LAU to the interface. The LAUB module is
controlled by the line control unit. The two modules, LCUB and LAUB, which are used
together, are configured as follows:

• the LCUB module as IOPLAU (e.g. CONF IOP:IOP=IOPLAU-0, OST=ACT;)

• the LAUB module as LAU (e.g. CONF LAU:LAU=0, OST=ACT;).

The IOP:LAU is always used in pairs, with the two LCUBs being cross-connected to the
two LAUBs for reasons of operational reliability. A pair of IOP:LAUs is connected on one
side to two different BIOC, and on the other side has 2 x 2 = 4 serial interfaces with
BX.25/X.25 protocol, for the connection of 4 data lines (X25 LINK 0........3) using the
LAPB data transmission procedure (Link Access Procedure Balanced). The maximum data
transmission rate is 64 kbit/s.

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 EWSD Coordination Processor (CP)
1.3 Racks and Frames

Frames for the CP113C are located in standard racks with a height of 2450mm. Figure on
next page shows the equipment in the CP113C rack. Another rack is required to
accommodate additional equipment (Modems, magnetic tape drive).

CP113C module frames

Following types of module frames and a device frame are used in the CP113C:

• a module frame for processors (BAP, CAP), bus for common memory and common
memory (F:PBC)
• a module frame for processors (IOC, CAP) and input/output processors (F: PIOP) for
EWSD Classic or a module frame is used to employ up to three CAP or one CAP, one
IOC, one AMP (necessary for SSNC connection) and input/output processors
(F:PIOP(B)) for EWSD powernode
• a device frame for accommodating magnetic disk units, magneto-optical disk units and
power supply units (F:DEV(F)). The devices are pushed in the same way as modules.
Each device requires a plug-in converter.

The following table shows the modules in the CP113C and their assignments to the
functional units :

Functional Module Name

unit
BAP, CAP, PEX Program execution
IOC
AMP AMPC To convert the ATM oriented data streams from SSNC to
the internal EWSD format & Vice Vesra
BCMY PIA Processor interface and arbiter
MTI Memory and tracer interface
BCM Bus clock generator and maintenance controller
IOP:MB IOPMB Input/output processor for message buffer
IOP:MB IOPMB/PB Input/output processor for message buffer with
possibility to connect a profi bus
IOP:TA IOPTA Input/output processor for time and alarm
IOP:UNI IOPUNI Input/output processor unified for O&M devices
IOP:LAU LCUB Line control unit, module B
LAUB Link adaption unit, module B

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EWSD Coordination Processor (CP)

Fuses MUT01

MUT02
F:PIOP2

C 1
F:PIOP0 A O IOPG 2 MUT03
P C
2
Fan
C I
AB O
C IOPG 0
PA MUT04
AC BCMY 0 CMY 0
2P P0
F:PBC0 0
MUT05
B C
A A BCMY 1 CMY 1
P P MUT06
G:PBC1 1 1

C I
A O IOPG 1 MUT07
P C
F:PIOP1 3 1

Fan MUT08
C I
A O IOPG 3
P C MUT09
F:PIOP3 5 3

M M M M

O D D O MUT10
F:DEV(F) D D D D

0 0 1 1
MUT11
Fan with air filter

Rack for CP 113C for EWSD Classic

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EWSD Coordination Processor (CP)

MUT 01 FUSE

C C C
MUT 02 A A A F: PIOP(B)
P P P
4 6 8

A C I IOP
MUT 03 M A O Group 0
P P C F: PIOP(B)
0 2 0

MUT 04 FAN

B C
MUT 05 A A BCMY CMY
P P 0 0 F: PBC
0 0

B C BCMY CMY
A A F: PBC
MUT 06 1 1
P P
1 1
A C I IOP
MUT 07 M A O
Group 1 F: PIOP(B)
P P C
1 3 1
MUT 08 FAN
C C C
MUT 9 A A A F: PIOP(B)
P P P
5 7 9

M M M M
MUT 10 O D D O
D D D D
0 0 1 1
MUT 11
FAN BOX

Rack for CP113C for EWSD Powernode

ALTTC / SW-II 22 /50 F15 - CP/ 1.10.2005

 C101 DCCM C/D C101 DCCM C/D
C101 DCCM C/D

CAP

AMP
CAP/
BAP
C119 PEX / AMPC C119 PEX
C117 PEX

C131 DCCM C/D C127 DCCM C/D

C125 DCCM C/D

CAP

IOC
B:IOC- ADDR
C149 PEX

B:IOC- ADDR
EWSD

C145 PEX
C161 DCCM C/D C143 PEX

IOC
C153 LAUB

CAP CAP/
C179 PEX C151 DCCM/D

ALTTC / SW-II
C165 LCUB

11
C191 LAUB C167 BCM

C199 LCUB C177 LAUB

11
C207 LAUB
C189 LCUB

15

15
C215 LCUB

*
C201 PIA - 0

C227 LAUB C199 LAUB

Module Frame for F:PIOP

Module Frame for F:PBC

* Optional IOP:UNI
C217 PIA - 1

* Optional IOP:UNI
C235 LCUB

14
14
BCMY
C211 LCUB

*
C243 LAUB
C233 PIA - 2

Module Frame for F:PIOP(B)

C221 LAUB
C251 LCUB

13

23 /50
IOPG
C233 LCUB C249 PIA - 3

*
13

IOPG
C263 LAUB C257 MTI

12
C243 IOP:UNI

C271 LCUB

7
2
C255 IOP:MB / CCNC

C281 IOP:: UNI C287 CMYC

12
C269 IOP:MB/ MBG 1 or 3

1
C289 IOP:MB / CCNC

2
CM YM- 1
C295 CMYM- 0

C297 IOP:TMB / MBG 1 or 3

1
C279 IOP:MB / MBG 0 or 2

0
CM YM- 2
C305 IOP:MB / MBG 0 or 2 C307 CM YM- 1

0
CMY

10
C291 IOP:MB / SYPC
C313 IOP:MB / SYPC/ PB

10
C319 CM YM- 2
9

C301 IOP:MB / CCG

C321 IOP:MB / CCG

9
8

C329 IOP:TA C311 IOP:TA C331 CM YM- 3

F15 - CP/ 1.10.2005

Coordination Processor (CP)

C339 DCCM C/D

C341 DCCM C/D C337 DCCCM C/D
EWSD Coordination Processor (CP)
2.0 Software

The EWSD software is 100% modular. The software functional units

form the top level of the hierarchy. Each software functional unit is made up of
logically related subsystems. The subsystems are in turn subdivided into one or
more modules. The modules are the smallest software units. They implement
the procedures, processes and data.

The processor concept of the CP113 is based on a distribution of

functions between the base processors (BAP), the call processors (CAP) and the
input/output controls IOC. The BAPM and the BAPS have the same software
functional units (Fig. 3.1). The CAPs contain mainly software for performing
their call processing functions. The IOCs only contain firmware.

BAPM/BAPs CAP IOP

CP organization
CP input/output control CP organization (kernel)
CP safeguarding CP safeguarding (local)
CP call processing CP call processing Firmware (only)
CP administration CP input/output control
CP maintenance (IOCP)
CP utilities

The CPFig.
organization functional
3.1 : Software unit of the
in the processor CPCP113
of the software comprises the
operating system and the loader. Each processor in the EWSD has its own
operating system. The capabilities of the operating system are dependent on the
functions performed by the processor and the resources it is required to
administrate. All the operating systems must perform their functions under
real-time conditions. They are therefore interrupt driven under real time
conditions. The software necessary to operate an exchange is stored in load
libraries (loadlibs) on the system disks and must be transferred to the CP using
the loaders in the programs. Some of the loaders are loaded in the common
memory of the CP during the bootstrap procedure. The other programs
required to start the processor are stored in a PROM (programmable read-only
memory).

The CP input/output control functional unit of the CP software is

responsible for physical input/output (PIO), logical input/output (LIO),

ALTTC / SW-II 24 /50 F15 - CP/ 1.10.2005

EWSD Coordination Processor (CP)
message exchanges between the CP user processes and the call processing
periphery (IOCP), file control (FCP) and the update function.

The functions of the CP safeguarding functional units of the CP software

are firstly to isolate and eliminate faults in the system, and secondly to set a
workable configuration after system recovery.

The CP call processing functional unit of the CP software is responsible

for the central call processing functions (e.g. digit translation, routing
administration). Its tasks include sending setting instructions to the switch
group control and to the GPs in the LTGs.

The CP administration functional unit of the CP software processes the

administrative MML commands and saves The charge, statistical and traffic
data in the external memories. This data is made available by the call
processors. The CP sends messages to the peripheral processors for further
processing.

The CP maintenance functional unit of the CP software processes

messages concerning measurement, test and diagnostic results of the LTGs. It
processes the system-internal alarm messages and MML commands which
ensure trouble-free operation. This functional unit is also responsible for
indicating faults on the system panel (SYP) and generating audible alarms if
necessary.

The CP utilities functional unit of the CP software makes test programs

available for error location, analysis and correction in the software.

ALTTC / SW-II 25 /50 F15 - CP/ 1.10.2005

EWSD Coordination Processor (CP)

3.0 Functions
3.1 Call Processing Functions

The most important call processing functions of the CP are as follows:

- digital translation,
- routing administration,
- zoning,
- path selection in the switching network,
- call charge registration,
- traffic data administration,
- network management.

The call processing functions are implemented in the CP call processing

functional unit of the software. The results of the call processing activities, such
as the charge and traffic data, are recorded and administrated by the CP
administration functional unit.

The call processing process in the CP is run in an endless loop. It re-

ceives the messages which are sent to it, processes them and sends commands to
the appropriate devices. Most of the time, the call processing process is
required to deal with several parallel tasks.

When handling several calls simultaneously, the call processing process

uses memory areas to store the transient data for future call control. The
transient data includes the states of the current calls.

The messages, e.g. "seize calling party", are supplied from a group
processor via the input/output processor for the messages buffer to the input list
for call processing messages. The current process in the CP is interrupted at
regular intervals, and a call processing message is transferred from the input
list to the call processing process. The message is processed by means of a
state/event combination: the stored state of a subscriber line or a interoffice
trunk is combined with the new event and the corresponding processing
procedure is invoked. The state changes if the event is processed successfully.

The next call processing event encounters the new state. This
combination causes another processing procedure, which corresponds to the
new state change, to be invoked. The connection is set up progressively in this
manner and finally completed. It is cleared down again analogously.

The call processing functions are described in detail below:

ALTTC / SW-II 26 /50 F15 - CP/ 1.10.2005

EWSD Coordination Processor (CP)

When a connection is set up, a digit block ( of the dialed digit) is

transferred to the CP by the LTG. The CP performs a digit translation using
these digits. The result of digit translation is the desired destination. If the call
is an external one, the CP subsequently determines an idle trunk to the
destination with the aid of the routing administration function.

The zoning function of the CP determines the zone in which the

destination is located. The current tariff for call charge registration is
determined from the zone in the line/trunk group.

A connection must then be set up from the calling subscriber line to the
desired destination via switching network. The busy or idle status of the
switching network is saved in the database of the CP for this purpose. The path
through the switching network is determined by path selection function. The
switch group control is informed of this path data by means of command via
an output list and the input/output processor for the message buffer.

The call charge registration function is distributed between the

line/trunk groups and the CP. The line/trunk group sums up the meter pulses
during a call. The meter pulses determined in the line/trunk groups are
transmitted to the CP either at the end of the call or at regular intervals in the
case of long call. The CP saves the meter pulses in the calling subscriber's
personal meter. It makes the charge data available for further processing when
instructed to do so by the operating personnel.

The traffic data administration function are subdivided into traffic

measurement, traffic supervision, traffic observation and traffic structure
measurement. The traffic data is crucial to the carrier for traffic handling and
traffic forecasting. Several traffic data administration programs are available
in the CP. These programs gather and process the traffic data of all the
different areas of the switching center and the trunk groups.

The network management function protects the network and the

switching center against overload condition, or if they do become overloaded,
takes suitable steps (traffic restrictions) to prevent the network from collapsing.
The function also permits traffic to be distributed flexibly between the available
paths and trunk groups, according to specific criteria.

ALTTC / SW-II 27 /50 F15 - CP/ 1.10.2005

 EWSD Coordination Processor (CP)
3.2 Operation & Maintenance Functions

The operation & maintenance terminals (OMT) in the operation and

maintenance center (OMC) are the access points for all operation and
maintenance functions. A local OMT is provided in the switching center for
performing these tasks.

The OMTs in the operation & maintenance center are connected to the
CP113 either via the data communication processor (DCP) and data lines or
directly via the IOP:SCDP. The local OMT is also connected to the CP directly.

The standard man-machine language (MML) of the CCITT is used for

the dialog between the operating personnel and the CP. The CP controls the
dialog with OMT and checks that commands are entered correctly.

The operation and maintenance functions are incorporated in the CP

administration and CP maintenance functional units of the software.The
operating procedures for the many different tasks which can be handled via
the OMT are described in separate operation manuals.

3.3 Safeguarding functions

The CP contains number of safeguarding programs the CP

safeguarding functional unit of the software, which are designed to ensure the
operability and availability of the switching center. These safeguarding
programs analyze both faults affecting the CP itself and faults in the other
subsystems. The safeguarding software in the CP does not merely respond to
faults, but also starts test and diagnostic programs. The functions of the
safeguarding programs are to:

- determine and set a workable configuration after system recovery,

- record and process safeguarding messages from the periphery and

the CP processes,

- control the periodic test procedures,

- evaluate the alarm messages from the supervisory circuits in

the CP,

- gather and save fault symptoms,

- analyze and localize faults,

ALTTC / SW-II 28 /50 F15 - CP/ 1.10.2005

EWSD Coordination Processor (CP)

- restore a workable system configuration after a hardware fault,

- eradicate the consequences of software errors by means of

adequate recovery actions, if these errors cannot be cleared by
the user programs themselves.

Three different recovery types are implemented in EWSD. They are as

follows:

* Installation recovery

An installation recovery is performed when the system is put into service

during an initial installation, APS change or restoral procedure (e.g. after a
power failure).

* Central recovery

A central recovery is performed in order to restore call processing

operation after fault in the coordination processor area. It includes recovery
action which clears a fault during operation (both hardware faults and software
errors) and restores the full call processing capabilities immediately.

* Peripheral recovery

A peripheral recovery is performed when units belonging to the call

processing periphery are returned to service after a fault. It includes all
recovery action which clears a fault during operation (software errors) and
makes the unit concerned available to the system again. The call processing
peripheral units in which a peripheral recovery takes place include LTG, DLU
and CCNC.

ALTTC / SW-II 29 /50 F15 - CP/ 1.10.2005

 EWSD Coordination Processor (CP)

4. MML Commands

4.1 Interrogating CP Equipment

Interrogating CP equipment
STAT SSP :[UNITS = ] [ ,OST= ] ;
DISP SSP ;
DISP IOC : IOC= ;
DISP IOP : IOP= ;
Disp AMP ; (Only with EWSD Powernode)
DISP CAP ;
DISP MD;
DISPMTD : MTD= ;
DISP MT : { VSN= ,MTD= } ;
DISP MOD : MOD= ;
DISP MO : { VSN= ,MOD= } ;
DISP OMT : OMT= ;
DISP MTD : MTD= :
DISP MT : {VSN= , MTD= };

ALTTC / SW-II 30 /50 F15 - CP/ 1.10.2005

 EWSD Coordination Processor (CP)
X522/CTYCPZ1V1332/R03/003 00-03-17 18:03:54
3723 CA EWSD2000 3080/02056

STASSP ; EXEC’D

UNIT OST UNIT OST UNIT OST

- - - - - - - - - - - -+- - - - - - - - - - - - - - -+- - - - - - - - - - - - - - -+- - -
BAP-0 MAS BAP-1 SPR IOC-0 ACT
IOC-1 ACT CMY-0 ACT CMY-1 ACT
BCMY-0 ACT BCMY-1 ACT
IOPMB-0 ACT IOPMB-1 ACT IOPMB-32 ACT
IOPMB-33 ACT IOPMB-40 ACT IOPMB-41 ACT
IOPMB-42 ACT IOPMB-43 ACT IOPUNI-0 ACT
IOPUNI-1 ACT IOPTA-0 ACT IOPTA-1 ACT
IOPLAU-0 ACT IOPLAU-1 ACT LAU-0 ACT
LAU-1 ACT
MDD-0 ACT MDD-1 ACT MTD-0 PLA
MTD-1 PLA MOD-0 ACT MOD-1 PLA
OMT-0 *MBL OMT-1 *UNA X25LINK-0 ACT
X25LINK-1 ACT

END JOB 3723

X522/CTYCPZ1V1332/R03/003 00-03-17 18-:04:09

3730 CA EWSD2000 3080/08741

DISPSSP ; EXEC’D

UNIT PBI MEMSIZE FIRMWARE VERSIONS DATA

PHYS APS B-PART APS PART APS PART UP-TO-
(FE) PROM PEROM IN PART DATE
- - - - - +- - - - -+- - - - -- -- - - - - - - - -+- - - - - - - - - -- -+- - - - - - - - --- - -- - - - - - - - - - - - --
BAP-0 0 64 32 0302 0000 1330 0007 1330 0007 YES
BAP-1 2 64 32 0302 0000 1330 0007 1330 0007 YES
IOC-0 1 32 0206 0000 1330 0007 1330 0007 YES
IOC-1 3 32 0206 0000 1330 0007 1330 0007 YES
CMY-0 512 256 2300 1900 0043 1900 0043 YES
CMY-1 512 256 2300 1900 0043 1900 0043 YES
BCMY-0 0020 0000 0020 0000 YES
BCMY-1 0020 0000 0020 0000 YES

END JOB 3730

X522/CTYCPZ1V1332/R03/003 00-03-17 18:04:36

ALTTC / SW-II 31 /50 F15 - CP/ 1.10.2005

 EWSD Coordination Processor (CP)
3736 CA EWSD2000 3080/02067

DISPIOC:IOC=0 ; EXEC’D

IOC : IOC-0 PBI : 1

REDUNDANT IOC : IOC-1 PBI : 3

BIOC IOP BIOC IOP BIOC IOP

- - - - -------- --- -+-- -- - - -----------------+------ - - -- - - - - - - - - +- - -
2 IOPMB-0 0 IOPMB-32 9 IOPMB-40
10 IOPMB-42 8 IOPTA-0 11 IOPLAU-0
12 IOPUNI-0

END JOB 3736

X522/CTYCPZ1V1332/R03/003 00-03-17 18:04:54

3744 CA EWSD2000 3080/06749

DISPIOP:IOP=IOPUNI-X ; EXEC’D

IOC BIOC IOP OST LOADTP FEPROM

- - - - - - - - - - - -+- - - - - - - - - - --+- - - - -- - - - - - -+- -- - - - - -- - -- -+-- - - - - - - ------+-------- - -
0 12 IOPUNI-0 ACT 121 SYSTEM
1 12 IOPUNI-1 ACT 121 SYSTEM

END JOB 3744

X522/CTYCPZ1V1332/R03/003 00-03-17 18:05:05

3749 CA EWSD2000 3080/03652

DISPIOP:IOP=IOPLAU-X ; EXEC’D

IOC BIOC IOPLAU OST LAU OST CHAN0 CHAN1 LDTYP LDPRTY IOPLAUR
- - - --+- - - - -+- - -- - - - - +- - - -+- ---- -+- -- -+- - - - -- -- -+- - - -- - - -+- - - - - - - -+- --- - - - - -+--- - - -- -
0 11 0 ACT 0 ACT X25LINK-1 X25LINK-1 100 LOW 1
1 11 1 ACT 1 ACT 100 LOW 0

END JOB 3749

X522/CTYCPZ1V1332/R03/003 00-03-17 18:09:05

3757 CA EWSD2000 2970/01770

ALTTC / SW-II 32 /50 F15 - CP/ 1.10.2005

 EWSD Coordination Processor (CP)

DISPMD ; EXEC’D

VSN DISK SIZE FREE RAM PAGES FREE F1 LABELS NO OF FILES

- - - - - - - - - - - -+- - - - - - - - - -- - +- - - - - - - - - - - - - - - - -+- - - - - - - - - - - - - - - - -+- -- - - - - - - - - -
VSN0 00 2211710 1494846 8 442
VSN0 01 2211710 1501278 9 441

END JOB 3757

X522/CTYCPZ1V1332/R03/003 00-03-17 18:13:14

3942 CA EWSD2000 2970/08390

DISPMO:VSN=SAVMOD ; EXEC’D

VSN = SAVMOD OWNER = X566 CODE = EBC NORM = 1

END JOB 3042

X522/CTYCPZ1V1332/R03/003 00-03-17 18:14:04

3950 CA EWSD2000 3080/08410

DISPMOD:MOD=0 ; EXEC’D

UNIT TOP SCSIADDR

- - - - - - -- - - - - -+ - - - -- - - - - - -+- -- - - - - - -
MOD-0 IOPUNI-0 2
END JOB 3950

X522/CTYCPZ1V1332/R03/003 00-03-17 18:09:02

3811 CA EWSD2000 3080/06750

DISPOMT:OMT=X ; EXEC’D

UNIT TOP CHAN BAUDRATE CONNECT HANDSHK FAULT INFORMATION

- -- - - -+- -- - - +- - - - - -+- -- - - - - - - - -+- - - - - - - - - +- - - - - - - - - -+- - - - - - - -+- - - -- - - - -- - -- -
OMT-0 IOPUNI-0 0 9600 DIRECT YES
OMT-1 IOPUNI-1 0 9600 DIRECT YES
END JOB 3811

4.2 Configuring CP Components

ALTTC / SW-II 33 /50 F15 - CP/ 1.10.2005

EWSD Coordination Processor (CP)
Configuring CP components
CONF BAP : [ BAP= ] ,OST= [, DIAG= ] [ ,SUP= ] ;
COM BAP ;
CONF CAP : CAP= ,OST= [ ,DIAG= ] [ ,SUP= ] ;
CONF AMP : AMP= , OST= [ ,DIAG=] [, SUP= ] ;
COM AMP ;
CONF BCMY : [BCMY= ] ,OST= [ ,DIAG= ] [ ,SUP= ] ;
CONF CMY : [ CMY= ] ,OST= [ ,DIAG= ] [ ,SUP= ] ;
CONF IOC : IOC= ,OST= [ ,DIAG= ] [ ,SUP] ;
CONF IOP:IOPP= ,OST= ;
CONF IOPG:IOC= ,OST=;
CONF LAU : LAU= ,OST= ;
CONF MDD : MDD= ,OST= ;
CONF MOD : MOD= ,OST= ;
CONF MTD : MTD= , OST= ;
CONF OMT : OMT= ,OST= ;

OST = ACT/MBL Operating state

DIAG = YES/NO If YES is input, diagnosis is performed
SUP = YES/NO If YES is input, output of progress message is supressed

If a unit could be configured as specified in the command, the associated

output contains the acknowledgment EXEC’D and the operating states before and
after configuration.

The outputs from executed CONF commands are also written into the
HF.ARCHIVE file.

It is possible for units to be marked as NAC in the system-internal

configuration table. This means that unit in question is in ACT but is not accessible
because the preceding unit has a state other than ACT.

TIP

The BAP which is currently the master can not be configured to MBL directly To
configure him, change the master/spare status with the command COMBAP; first.

MAS SPR

ALTTC / SW-II 34 /50 F15 - CP/ 1.10.2005

UNA MBL
 EWSD Coordination Processor (CP)

CONFBAP : BAP= , OST=ACT;

or
CONFBAP : BAP= , OST=SPR;

522/CTYCPZ1V1332/R03/003 00-03-17 18:11:01

3847 CA EWSD2000 2967/00045

CONFBAP:BAP=1, OST=ACT ; ACCEPTED

END TEXT 3847

X522/CTYCPZ1V1332/R03/003 00-03-17 18:11:41

3847 CA EWSD2000 3076/02052 HF .ARCHIVE-05199

CONFBAP:BAP=1, OST=ACT; EXEC’D

CONFIGURATION BAP-1 FROM MBL TO SPR

END JOB 3847

X522/CTYCPZ1V1332/R03/003 00-03-17 18:15:19

3963 CA EWSD2000 2967/00045

COMBAP ; ACCEPTED

END TEXT 3963

X522/CTYCPZ1V1332/R03/013 00-03-17 18:16:15

3963 CA EWSD2000 3076/03204 HF .ARCHIVE-05200

COMBAP ; EXEC’D

UNIT OST
- - - - - - - - - - - -+- - -
BAP-0 SPR
BAP-1 MAS
END JOB 3963 ACT MBL

ALTTC / SW-II 35 /50 F15 - CP/ 1.10.2005

UNA
EWSD Coordination Processor (CP)

MSC2/D2MMPK1V9502-I21/310 98-12-14 14:20:09

6305 CA MARTIN#1 2967/00045

CONFBCMY : BCMY=1, OST=ACT ACCEPTED

END TEXT 6305

MSC2/D2MMPK1V9502-I21/110 98-12-14 14:21:34

6305 CA MARTIN#1 3076/02052

CONFBCMY : BCMY=1 ,OST=ACT ; ESEC’D

CONFIGURATION BCMY-1 FROM MBL TO ACT

END JOB 6305

MSC2/D2MMPK1V9502-I21/110 98-12-14 14:21:59

6316 CA MARTIN#1 2967/00045

CONFCMY:CMY=1 ,OST=ACT; ACCEPTED

END TEXT 6316

MSC2/D2MMPK1V9502-I21/110 98-12-14 14:23:42

CONFCMY : CMY =1 ,OST=ACT; EXEC’D

CONFIGURATION CMY-1 FROM MBL TO ACT

END JOB 6316

ALTTC / SW-II 36 /50 F15 - CP/ 1.10.2005

EWSD Coordination Processor (CP)

UNA UNA

UNA UNA
UNA

X522/CTYCPZ1V1332/R03/003 00-03-17 18:49:44

0242 CA EWSD2000 3076/02052 HF .ARCHIVE - 05226

CONFCAP : CA[=0 ,OST=MBL, DIAG=NO ; EXEC’D

CONFIGURATION CAP-0 FROM PLA TO MBL

END JOB 0242

ACT MBL

ALTTC / SW-II 37 /50 F15 - CP/ 1.10.2005

UNA PLA
EWSD Coordination Processor (CP)

X522/CTYCPZ1V1332/R03/013 00-03-17 18:21:30

4060 CA EWSD2000 2967/00045

CONFIOC : IOC=0 ,OST=ACT ; ACCEPTED

END TEXT 4060

X522/CTYCPZ1V1332/R03/013 00-03-17 18:22:13

4060 CA EWSD2000 3076/02052 HF .ARCHIVE-05206

CONFIOC:IOC=0 ,OST=ACT ; EXEC’D

CONFIGURATION IOC-0 FORM MBL TO ACT MASKNO:02052

MASKNO:06209

SYNCHRONIZING FROM MDD-1 TO MDD-0 : STARTED

END TEXT 4060

X522/CTYCPZIV1332/R03/013 00-03-17 18:30:13

4060 CA EWSD2000 3076/06210 HF .ARCHIVE - 05211

CONFIOC : IOC=0 , OST=ACT;

SYNCHRONIZING FROM MDD-1 TO MDD-0 :RUNNING

END JOB 4060

X522/CTYPZ1V1332/R03/013 00-03-17 18:35:41

4060 CA EWSD2000 3076/06210 HF .ARCHIVE-05241

ALTTC / SW-II 38 /50 F15 - CP/ 1.10.2005

EWSD Coordination Processor (CP)

CONFIOC:IOC = 0 ,OST=ACT ;

SYNCHRONIZING FROM MDD-1 TO MDD-0 : FINISHED

END JOB 4060

ACT MBL

UNA PLA

X522/CTYCPZ1V1332/R03/013 00-03-17 18:22:53

4085 CA EWSD2000 3076/02052 HF .ARCHIVE-05208

CONFIOP:IOP=IOPMB-33 ,OST=ACT; EXEC’D

CONFIGURATION IOPMB-33 FROM MBL TO ACT

END JOB 4085

ACT ACT
ALTTC / SW-II 39 /50 F15 - CP/ 1.10.2005
 EWSD Coordination Processor (CP)

0281
CAUTION : THE CONF IOPG COMMAND IS EXECUTED WITHOUT MASKNO : 12153
REDUNDANCY CHECK !
CHECK THE CONSEQUENCES OF YOUR COMMAND FIRST !
DO YOU WANT COMMAND TO BE EXECUTED ? (YES: +/NO:-) <
+

X522/CTYCPZ1V1332/R03/003 00-03-17 18:52:12

0281 CA EWSD2000 2967/00045

CONFIOPG : IOC=1 ,OST=MBL ; ACCEPTED

X522/CTYCPZ1V1332/R03/003 00-03-17 18:52:1502

0281 CA EWSD2000 3076/02053 HF .ARCHIVE-05229

CONFIOPG : IOC=1 ,OST=MBL ; EXEC’D

CONFIGURATION

UNIT FROM TO
- - - - - - - - - - - -+- - - - - - - - - - - -+- -
IOPMB-1 ACT MBL
IOPMB-33 ACT MBL
IOPMB-41 ACT MBL
IOPMB43 ACT MBL
IOPTA-1 ACT MBL
IOPLAU-1 ACT MBL
IOPUNI-1 ACT MBL
END JOB 0281

WARNING

CONFIOPG is an extremely dangerous command, because no redundancy check is made!

This means that it is possible to block all IOP on all IOC which leads to an ISTART! This
command is only needed to diagnose all IOP belonging to an IOC simultaneously.

X522/CTYCPZ1V1332/R03/013 00-03-17 18:34:22

4266 OMT-01/EWSD2000 2967/00045

CONFLAU:LAU=0, OST=ACT ; ACCEPTED

ALTTC / SW-II 40 /50 F15 - CP/ 1.10.2005

EWSD Coordination Processor (CP)

END TEXT JOB 4266

X522/CTYCPZ1V1332/R03/013 00-03-17 18:34:26

4266 OMT-01/EWSD2000 3076/02052 HF .ARCHIVE-05212

CONFLAU:LAU=0 ,OST=ACT; EXEC’D

CONFIGURATION LAU-0 FROM MBL TO ACT

END JOB 4266

ACT MBL

UNA PLA

X522/CTYCPZ1V1332/R03/003 00-03-17 18:41:50

0107 OMT-01/EWSD2000 2967/00045

CONFMDD:MDD=1, OST=ACT; ACCEPTED

END TEXT 7269

X522/CTYCPZ1V1332/R03/003 00-03-17 18:42:12

0107 OMT-01/EWSD2000 3076/02052

CONFMDD:MDD=1, OST=ACT; EXEC’D

CONFIGURATION MDD-1 FROM MBL TO ACT MASKNO:02052

ALTTC / SW-II 41 /50 F15 - CP/ 1.10.2005

EWSD Coordination Processor (CP)
MASKNO:06209
SYNCHRONIZING FROM MDD-0 TO MDD-1 : STARTED

END TEXT 7269

X522/CTYCPZ1V1332/R03/003 00-03-17 18:44:12

0107 OMT-01/EWSD2000 3076/06210

CONFMDD:MDD=1 ,OST=ACT ;

SYNCHRONIZING FROM MDD-0 TO MDD-1 : RUNNING

END TEXT 7269

X522/CTYCPZ1V1332/R03/003 00-03-17 18:56:34

0107 OMT-01/EWSD2000 3076/06210

CONFMDD:MDD=1, OST=ACT ;

SYNCHRONIZING FROM MDD-0 TO MDD-1 : FINISHED

END JOB 7269

ACT MBL

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UNA PLA
 EWSD Coordination Processor (CP)

X522/CTYCPZ1V1332/R03/003 00-03-17 18:41:50

0107 OMT-01/EWSD2000 3079/02054

CONFOMT:OMT=1, OST=ACT; EXED’D

CONFIGURATION OMT -1 FROM MBL TO ACT

END JOB 0107

4.3 Diagnose CP Components

DIAG BAP : [BAP= ], [ , SUP= ] ;

DIAG BAP : [BAP= ], REP= [ ,INT= ] [ , STATCS= ] ;
DIAG CAP : CAP= , [ , SUP= ] ;
DIAG CAP : CAP= ,REP= [ ,INT= ] [ , STATCS= ] ;
DIAG AMP : AMP= , [ , SUP= ] ;

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EWSD Coordination Processor (CP)
DIAG AMP : AMP= ,REP= [ ,INT= ] [ , STATCS= ] ;
DIAG BCMY : [BCMY = ], [ , SUP= ] ;
DIAG CMY: [CMY=] [ , SUP=] [ ,ONEBIT= ];
DIAG IOC : IOC= [ , SUP= ];
DIAG IOC: IOC= , REP= [ , INT= ] [ , STATCS= ];
DIAG IOP : IOP= ;
DIAG IOP : IOP= , REP= [,INT= ] [,STATCS= ] ;
DIAG IOPG : IOC= ;
DIAG LAU : LAU= [ ,SUP= ] ;
DIAG LAU : LAU= , REP= [ , INT= ] [ , STATCS= ] ;
DIAG MDD : MDD= [ ,SUP= ] [ ,TA= ] ;
DIAG MDD : MDD= ,REP= [ ,INT= ] [ ,STATCS= ] [ ,TA= ] ;
DIAG MOD : MOD= [ ,SUP= ] [ ,LABELMO= ] ;
DIAG MOD : MOD= ,REP= [ ,INT= ] [ , STATCS= ] ;
DIAG MTD : MTD= [ ,SUP= ] ;
DIAG MTD : MTD= ,REP= [ ,INT= ] [ ,STATCS= ] ;
DIAG OMT : OMT= [ ,SUP= ] ;
DIAG OMT : OMT= ,REP= [ ,INT= ] [ ,STATCS= ] ;

Most of the CP components can be diagnosed in two ways. A single diagnosis and repeated
diagnosis. The repeated version can be executed permanently with the Parameter
REP=PERM or 2 to 65535 times with e.g. REP=15.

TIP
• To diagnose a CP component it must be configured to MBL first. Because the
BAPM can not be configured to MBL, the command COMBAP; has to be executed
to change the master/spare status. Then the new BAPS must be configured to MBL
and diagnosis can be started.

• A TEST command exists beside the DIAG command for most of the CP components
. If you want to use the TEST command (sometimes less strong checking than in
case of DIAG), the tested unit (and, if available, the redundant unit) has to be in
operation.

X522/CTYCPZ1V1332/R03/003 00-03-17 18:44:21

0153 OMT-01/EWSD2000 3076/02287 HF .ARCHIVE-05223

DIAGBAP:BAP=1, SUP=N; EXEC’D

END OF DIAGNOSIS WITH PAILURE MMN:CP900-0000

OST=MBL

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 EWSD Coordination Processor (CP)
FAULT LOCATION:

UNIT MODULE MOUNTING LOCATION

- - - - - - - - - - - -+- - - - - - - - - - - - - - - - - +- - - - - - - - - - - - - - - - - -
BAP-1 PEX C006C117

END JOB 0153

X522/CTYCPZ1V1332/R03/003 00-03-17 18:50:10

0249 CA EWSD2000 2967/00045

DIAGCAP:CAP=0 ; ACCEPTED

END TEXT 0249

X522/CTYCPZ1V1332/R03/003 00-03-17 18:50:19

0249 CA EWSD2000 3076/02059

DIAGCAP:CAP=0; EXEC’D

END OF DIAGN. WITHOUT FAILURE

END JOB 0249

4.4 Creation of CP Hardware

Creation of CP hardware
CR CAP : CAP= ,PBI= ;
CR IOC : IOC= ,PBI= ,IOCR= ,PBIR= ;
CR AMP : AMP= ,PBI= , AMPR= , PBIR= ;
CR IOP : IOC= ,BIOC= ,IOP=IOPLAU-y ,IOPR= ,BIOCR= [ ,LOADTP= ]
[ ,LDPRTY= ] [ ,EAI= ];
CR IOP : IOC= ,BIOC= ,IOP=IOPMB-y ,SUBST= ;

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 EWSD Coordination Processor (CP)
CR IOP : IOC= ,BIOC= ,IOP= IOPUNI-y [ ,LOADTP= ];

4.4.1 Creation of CAP, IOC and AMP

To create CAP, IOC or AMP, the physical bus interface numbers (PBI), and for AMP and
IOC the corresponding number of the redundant AMP/ IOC (PBIR) are needed. The used
values are shown on next page.

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EWSD Coordination Processor (CP)
EWSD Classic

Assignment of physical bus interface numbers to call processor numbers

CAP PBI CAP PBI
0 4 3 9
1 6 4 10
2 8 5 11

Assignment of physical bus interface numbers to Input/output controllers

IOC PBI IOCR PBIR
0 1 1 3
1 3 0 1
2 5 3 7
3 7 2 5

EWSD Powernode

Assignment of physical bus interface numbers to call processors (CAP)

CAP PBI
0 4
1 6
2 12
3 13
4 10
CAP PBI
5 11
6 14
7 15
8 5
9 7

Assignment of physical bus interface numbers to input/output controllers

(IOC)
IOC PBI IOCR PBIR
0 1 1 3
1 3 0 1

Assignment of physical bus interface numbers to ATM bridge processors ( AMP)

AMP PBI AMPR PBIR
0 8 1 9
1 9 0 8

X522/CTYCPZ1V1332/R03/003 00-03-17 18:49:01

0228 CA EWSD2000 3098/00007

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 EWSD Coordination Processor (CP)
CRCAP:CAP=0 ,PBI=4 ; EXEC’D

END JOB 0228

Input/output processor for x. 25 link adaption unit

The creation of an IOPLAU requires parameters for the redundant unit. Since the EWSD
powernode is connected via Ethernet to OMC /NMC, the IOCLAU is not mandatory.

Input/output processor for x. 25 link adaption unit

IOPUNI-0/1 with the initial loading (boot) devices can neither be created nor be cancelled.

Tip

The optional parameter LOADTP in the commands for creating IOPLAU or IOPUNI is
used to define the software needed for this IOP types. Normally the default values are used.
The software loaded into these devices correspond to the name of the system file on disk,
e.g. SY. PSW. T100 for IOPLAU or SY. PSW. T121 for IOPUNI.

Following tables show parameter values for creation of IOPLAUs / IOPUNIs:

Parameter values for creation of IOPLAUs

IOP IOC BIOC IOPR BIOCR
IOPLAU-0 0 11 IOPLAU-1 11
IOPLAU-1 1 11 IOPLAU-0 11
IOPLAU-2 0 13 IOPLAU-3 13
IOPLAU-3 1 13 IOPLAU-2 13

Parameter values for IOPUNIs

IOP IOC BIOC
IOPUNI-0 0 12
IOPUNI-1 1 12
0 or 1 13....15
IOPUNI-2......7
2 or 3 12...15

Input/output processor for message buffer

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EWSD Coordination Processor (CP)
IOPMB get numbers depending on the hardware type and unit they are connected to (MB,
CCG and for EWSD classic also CCNC, SYP). For every IOPMB a redundant unit must be
specified. The used values can be found in following tables.

EWSD Classic

Parameter values for creation of IOPMBs

Connected IOP IOC BIOC SUBST
unit
IOPMB-0 0 2 IOPMB-1
CCNP
IOPMB-1 1 2 IOPMB-0
IOPMB-32 0 0 IOPMB-33
MBG00 /
MBG10 IOPMB-33 1 0 IOPMB-32

IOPMB-34 0 1 IOPMB-35
MBG01 /
MBG11 IOPMB-35 1 1 IOPMB-34

IOPMB-36 2 0 IOPMB-37
MBG02 /
MBG12 IOPMB-37 3 0 IOPMB-36

IOPMB-38 2 1 IOPMB-39
MBG03 /
MBG13 IOPMB-39 3 1 IOPMB-38

IOPMB-40 0 9 IOPMB-41
CCG
IOPMB-41 1 9 IOPMB-40
IOPMB-42 0 10 IOPMB-43
SYP
IOPMB-43 1 10 IOPMB-42

EWSD Powernode

Parameter values for creation of IOPMBs

Connected IOP IOC BIOC SUBST
unit

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 EWSD Coordination Processor (CP)
IOPMB-32 0 0 IOPMB-33
MB 0 / 1
IOPMB-33 1 0 IOPMB-32
IOPMB-34 0 1 IOPMB-35
MB 0 / 1
IOPMB-35 1 1 IOPMB-34
IOPMB-42 0 10 IOPMB-43
MB 0 / 1
IOPMB-43 1 10 IOPMB-42
IOPMB-00 0 2 IOPMB-01
MB 0 / 1
IOPMB-01 1 2 IOPMB-00
IOPMB-40 0 9 IOPMB-41
CCG
IOPMB-41 1 9 IOPMB-40

4.5 System Splitting Commands :

• SPLIT SSP :
This command is used to split the system. When the system is split he BAP spare
is the non switching BAP. The syntax of the command will be

SPLIT SSP: [, [TEST=] [, SUP=] ];

TEST = YES/NO If YES is input all active CP units are

tested before the system is split.
SUP = YES/NO If YES is input, output of progress
message is suppressed.

* MERGE SSP

This command is used to cancel the split state of the system. An automatic
short test is performed on the input/output processors before they are reunited with
the system, peripheral devices are reunited without diagnosis. The syntax of the
command will be:

ALTTC / SW-II 50 /50 F15 - CP/ 1.10.2005

 EWSD Coordination Processor (CP)

MERGE SSP: [ , [TEST=] [, SUP=] ];

TEST = YES/NO If YES is input , the central units of the

non-switching part of the system are
diagnosed before it is merged with the
rest of the system.
SUP = YES/NO If YES is input,output of progress
message is suppressed.

5 Exercises

Please answer the following questions:

• Which switching task does the CP implement?

• Name the fundamental units of the CP113C.
• Which units can be accessed by the CP via the IOP : MB?
• Which units can be accessed by the CP via the IOP:UNI?
• Why is the processing unit (PU) duplicated in all processors (BAP,CAP and IOC)?
• Do call processing programs run on the basic processor master (BAPM)?
• Perform following configuration jobs:
a) BAPM to MBL
b) IOPMDD0 from the ACT to MBL
c) OMT0 from ACT to PLA.
• Display all subunits of CP113 which are in MBL
• Find out the units which are in status NAC.

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