EE 105 Spring 1997

Lecture 37

Small-Signal Analysis of CMOS Two-Stage Op Amp

I

Cascade two-port models of differential amplier with current-mirror supply
(input stage) and common-source amplier with current supply (second gain
stage)

I

First stage:
polarity of

G

m

1

is inverted to reect reversal of input terminals ... which is done
to make the overall gain positive for

v

d

> 0

G

m

1

=

g

m

1



R

out

1

=

r

o

2

||

r

o

4

I

Second stage:

G

m

2

=

g

m

5

R

out

=

r

o

5

||

r

o

6
R
out1
v
i+
v
i
R
out
G
m1
v
d
G
m2
v
i2
v
d
+

v
o
+

v
i2
+

a
vdo
G
m1
R
out1
( ) G
m2
R
out
( ) =
a
vdo
g
m1
r
o2
r
o4
( )g
m5
r
o5
r
o6
( ) =

EE 105 Spring 1997
Lecture 37

Two-Stage CMOS Design Example

I

Design constraints
Typical situation for an internal op amp: area and power are both limited.
Simplied area constraint -- set

W

max

= 150

m
(for minimize channel-length modulation, set

L

min

= 3

m)
Set DC power budget at 1.25 mW (including reference current) for case where
we have symmetrical supplies:

V

+

= 2.5 V and

V

-

= - 2.5 V.

I

Initial Transistor Sizing:
Make (

W

/

L

)

1

= (150

m / 3

m) in order to maximize

G

m

1

and maximize
common-mode input voltage range
DC currents: assume

I

REF

= 50

A
Set DC bias current of differential amplier = DC bias of common-source stage
= 100

A each as a rst-cut --> total current drawn is 250

A --> power spec. is
just met
Transistor dimensions: (

W

/

L

)

5

= (150

m / 3

m) to maximize

g

m

5


Therefore (

W

/

L

)

3,4

= (

W

/

L

)

5

/2 = 25 -->

W

3,4

= 75

m since we use

L

min

to save
area.
For symmetrical output swing, we set (

W

/

L

)

6

= (W/L)
5
= (150 m / 3 m)
To maximize common-mode input range, we also set (W/L)
7
= (150 m / 3 m)
W L ( )
5
2 W L ( )
3 4 ,
----------------------------
I
D6

I
D7
------------
100 A
100 A
------------------- 1 = = =
EE 105 Spring 1997
Lecture 37
First-Cut CMOS Two-Stage Op Amp
M
8
(75/3)
50 A
M
3
(75/3)
v
I
v
I+
C
L
C
c
M
4
(75/3)
+2.5 V
2.5 V
A

n
C
ox
= 50
V
TOn
= 1.0 V

n
= 0.6 V
1/2
t
ox
= 15 nm

n
=
2
p
= 0.8 V
C
ov
= 0.5 fF/m
C
jno
= 0.1 fF/m
2
C
jswno
= 0.5 fF/m

Bn
= 0.95 V
m
jn
= 0.5
m
jswn
= 0.33
_
+
M
7
(150/3)
M
6
(150/3)
M
2
(150/3)
M
5
(150/3)
M
1
(150/3)
v
O
+

V
2
0.1(m/V)
L
A

p
C
ox
= 25
V
TOp
= 1.0 V

p
= 0.6 V
1/2
t
ox
= 15 nm

p
=
2
n
= 0.8 V
C
ov
= 0.5 fF/m
C
jpo
= 0.3 fF/m
2
C
jswpo
= 0.35 fF/m

Bp
= 0.95 V
m
jp
= 0.5
m
jswp
= 0.33
V
2
0.1(m/V)
L
n-channel MOSFET
p-channel MOSFET
1
2
3
4
EE 105 Spring 1997
Lecture 37
DC Bias Solution
I Assume that the DC input voltages are V
I+
= V
I-
= 0 V and V
O
= 0 V
I Input common-mode voltage range
room for improvement in the upper limit -- possible at the expense of increased
area (W/L) ratios must be increased.
I Output voltage swing
output range in nearly symmetrical and adequate
V
IC,max
2.5 V 1 V ( ) 1.28 V 1.4 V 0.82 V = =
V
IC,min
2.5 V 1.28 V 1 V ( ) + + 2.22 V = =
V
O,max
2.5 V 0.4 V 2.1 V = =
V
O,min
2.5 V 0.28 V + 2.22 V = =
EE 105 Spring 1997
Lecture 37
Small-Signal Performance
I Small-signal parameters:
g
m1
= g
m2
= 357 S
g
m5
= 2 g
m1
= 714 S
r
o2
= r
o4
= 600 k
r
o5
= r
o6
= 300 k
I Differential voltage gain:
in decibels, |a
vdo
|
dB
= 81 dB.
a
vdo
0.357 ( ) 600 600 ( ) 714 ( ) 300 300 ( ) 1.15
4
10 = =
EE 105 Spring 1997
Lecture 37
Stability -- A Brief Introduction
I Non-inverting, unity gain conguration
v
s
(t) = v
s
sin(
s
t)
Feedback is to negative terminal of op amp, which tends to stabilize the output
voltage v
o
(t) to be nearly equal to v
s
(t)
I What happens when the phase of a
vd
(j
s
) = 180
o
?
... the sign of a
vd
is ipped! Consider + and - terminals to be reversed!
... if |a
vd
(j
s
)| > 1, then the output is destabilized if the input is perturbed.
+
_
Op Amp
v
s
(t)
v
o
(t)
+
_
EE 105 Spring 1997
Lecture 37
Ensuring Stability
I If the gain of the op amp is less than 1 (in magnitude) when the phase is 180
o
,
then the unity-gain non-inverting configuation (worst-case) will be stable
I One solution: locate the second pole of the op amp
2
at approximately the unity
gain frequency
I The second gain stage is responsible for both poles
Device capacitances are lumped together in the circuit:
The compensation capacitor C
c
sets the dominant pole
1
by the Miller effect:
where R
1
= R
out1

2
a
vdo

R
1
R
out
C
1
C'
c
C'
L
I
s
G
m2
V
i2
V
o
+

V
i2
C
1
C
gs5
C
gd4
C
db4
C
gd2
C
db2
+ + + + =
C
L
C
L
C
db5
C
db6
C
gd6
+ + + =
C
c
C
c
C
gd5
+ =

1
1
R
1
C
1
R
1
1 G
m2
R
out
+ ( )C
c
+
EE 105 Spring 1997
Lecture 37
Second Pole Location
I Direct factoring of transfer function --> exact expression for
2
For the case when
I Interpretation:
At frequencies around
2
(>>
1
), the impedance Z
c
= (1 / j
2
C
c
) is small
enough that M
5
can be considered diode-connected
Load capacitance sees a Thvenin resistance of 1 / g
m5
-->

2
is set by the load capacitance in parallel with 1 / g
m5

I Adjusting compensation and load capacitors to satisfy
since G
m2
R
out
>> 1
C
1
C
c
, C
L

2
G
m2
C
L

1
1 G
m2
( )C
L

-------------------------------- =

2
a
vdo

2
G
m2
C
L

-----------
G
m1
R
out1
( ) G
m2
R
out
( )
R
1
C
1
R
1
1 G
m2
R
out
+ ( )C
c
+
------------------------------------------------------------------------ -
G
m1
R
out1
( ) G
m2
R
out
( )
G
m2
R
1
R
out
C
c

----------------------------------------------------------
C
c
C
L

G
m1
G
m2
-----------

EE 105 Spring 1997

Lecture 37
Capacitor Sizing
I The load capacitor is set by system specications: C
L
= 7.5 pF
with parasitic capacitances -->
I The compensation capacitor is approximately
the exact result is signicantly higher ...
I Area requirement with a 500 thick oxide is less than 100 x 100 m
2
-->
not a signicant addition to the op amp area
I Pole locations:
krad/s Mrad/s
I SPICE: must increase C
c
to 20 pF in order to have
krad/s Mrad/s
C
L
C
L
350 fF + 7.85 pF = =
C
c

357 S
714 S
------------------


C
L
3.9 pF =
C
c
5.3 pF =

1
5.8 =
2
67.2 =

2
a
vdo

1
1.3 =
2
10.4 =
EE 105 Spring 1997
Lecture 37