ENGI 242/ELEC 222 January 2004

Fixed Bias 1
BJT Fixed Bias
ENGI 242
ELEC 222
January 2004 ENGI 242/ELEC 222 2
BJT Biasing 1
For Fixed Bias Configuration:
Draw Equivalent Input circuit
Draw Equivalent Output circuit
Write necessary KVL and KCL Equations
Determine the Quiescent Operating Point
Graphical Solution using Loadlines
Computational Analysis
Design and test design using a computer simulation
ENGI 242/ELEC 222 January 2004
Fixed Bias 2
January 2004 ENGI 242/ELEC 222 3
Complete CE Amplifier with Fixed Bias
January 2004 ENGI 242/ELEC 222 4
Fixed Bias and Equivalent DC Circuit
ENGI 242/ELEC 222 January 2004
Fixed Bias 3
January 2004 ENGI 242/ELEC 222 5
Fixed-Bias Circuit
January 2004 ENGI 242/ELEC 222 6
DC Equivalent Circuit
ENGI 242/ELEC 222 January 2004
Fixed Bias 4
January 2004 ENGI 242/ELEC 222 7
Base-Emitter (Input) Loop
Using Kirchoffs voltage law: V
CC
+ I
B
R
B
+ V
BE
= 0
Solving for IB:
CC BE
B
B
V - V
I =
R
January 2004 ENGI 242/ELEC 222 8
Collector-Emitter (Output) Loop
Since: IC = IB
Using Kirchoffs voltage law: VCC + IC RC + VCE = 0
Because: VCE = VC VE
Since VE = 0V, then: VC = VCE
And VCE = VCC - IC RC
Also: VBE = VB - VE
with VE = 0V, then: VB = VBE
ENGI 242/ELEC 222 January 2004
Fixed Bias 5
January 2004 ENGI 242/ELEC 222 9
BJT Saturation Regions
When the transistor is operating in the
Saturation Region, the transistor is
conducting at maximum collector
current (based on the resistances in
the output circuit, not the spec sheet
value) such that:
CC CE
Csat
C
CE where
V - V
I =
R
V = 0.2 V
January 2004 ENGI 242/ELEC 222 10
Determining Icsat
ENGI 242/ELEC 222 January 2004
Fixed Bias 6
January 2004 ENGI 242/ELEC 222 11
Determining ICSAT for the fixed-bias configuration
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Load Line Analysis
ENGI 242/ELEC 222 January 2004
Fixed Bias 7
January 2004 ENGI 242/ELEC 222 13
Load Line Analysis
The end points of the line are : I
Csat
and V
CE
cutoff
For load line analysis, use VCE = 0 for ICSAT, and IC = 0 for VCEcutoff
I
Csat
:
V
CEcutoff
:
Where IB intersects with the load line we have the Q point
Q-point is the particular operating point:
Value of R
B
Sets the value of I
B
Where I
B
and Load Line intersect
Sets the values of V
CE
and I
C
.
CE
C
CC
Csat
V 0V
C
CE CC
I 0mA
V
I =
R
V = V
|
|
=
=
January 2004 ENGI 242/ELEC 222 14
Circuit values effect Q-point
ENGI 242/ELEC 222 January 2004
Fixed Bias 8
January 2004 ENGI 242/ELEC 222 15
Circuit values effect Q-point (continued)
January 2004 ENGI 242/ELEC 222 16
Circuit values effect Q-point (continued)
ENGI 242/ELEC 222 January 2004
Fixed Bias 9
January 2004 ENGI 242/ELEC 222 17
Load-line analysis
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DC Fixed Bias Circuit Example
ENGI 242/ELEC 222 January 2004
Fixed Bias 10
January 2004 ENGI 242/ELEC 222 19
Loadline Example Family of Curves
Emitter Stabilized Bias
ENGI 242
ELEC 222
ENGI 242/ELEC 222 January 2004
Fixed Bias 11
January 2004 ENGI 242/ELEC 222 21
BJT Emitter Bias
For the Emitter Stabilized Bias Configuration:
Draw Equivalent Input circuit
Draw Equivalent Output circuit
Write necessary KVL and KCL Equations
Determine the Quiescent Operating Point
Graphical Solution using Loadlines
Computational Analysis
Design and test design using a computer simulation
January 2004 ENGI 242/ELEC 222 22
Improved Bias Stability
The addition of RE to the Emitter circuit improves the stability of a transistor
output
Stability refers to a bias circuit in which the currents and voltages will
remain fairly constant over a wide range of temperatures and transistor
forward current gain ()
The temperature (TA or ambient temperature) surrounding the transistor
circuit is not always constant
Therefore, the transistor is not a constant value
ENGI 242/ELEC 222 January 2004
Fixed Bias 12
January 2004 ENGI 242/ELEC 222 23
Emitter-Stabilized Bias Circuit
Adding an emitter resistor to the circuit between the emitter lead and ground stabilizes
the bias circuit over Fixed Bias
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Base-Emitter Loop
ENGI 242/ELEC 222 January 2004
Fixed Bias 13
January 2004 ENGI 242/ELEC 222 25
Equivalent Network
January 2004 ENGI 242/ELEC 222 26
Reflected Input impedance of RE
ENGI 242/ELEC 222 January 2004
Fixed Bias 14
January 2004 ENGI 242/ELEC 222 27
Base-Emitter Loop
Applying Kirchoffs voltage law: - VCC + IB RB + VBE +IE RE = 0
Since: IE = ( + 1) IB
We can write: - VCC + IB RB + VBE + ( + 1) IB RE = 0
Grouping terms and solving for I
B
:
Or we could solve for IE with:
CC BE
B
B E
V - V
I =
R + (+1)R
B
CC E BE E E
R
- V + I + V + I R = 0
( + 1)

January 2004 ENGI 242/ELEC 222 28
Collector-Emitter Loop
ENGI 242/ELEC 222 January 2004
Fixed Bias 15
January 2004 ENGI 242/ELEC 222 29
Collector-Emitter Loop
Applying Kirchoffs voltage law: - VCC + IC RC + VCE + IE RE = 0
Assuming that I
E
I
C
and solving for VCE: VCE = VCC IC (RC + RE)
If we can not use IE IC the IC = IE and: VCE = VCC IC (RC + RE)
Solve for V
E
: VE = IE RE
Solve for V
C
: VC = VCC - IC RC
or
VC = VCE + IE RE
Solve for V
B
: VB = VCC - IB RB
or
VB = VBE + IE RE
January 2004 ENGI 242/ELEC 222 30
Transistor Saturation
CC CE
CSAT
C E
V - V
I =
R + R
At saturation, VCE is at a minimum
We will find the value VCEsat = 0.2V
For load line analysis, we use VCE = 0
To solve for ICSAT, use the output KVL
equation:
ENGI 242/ELEC 222 January 2004
Fixed Bias 16
January 2004 ENGI 242/ELEC 222 31
Load Line Analysis
The load line end points can be calculated:
At cutoff:
At saturation:
C
CE CC
I = 0 mA
V V | =
CE
CC
C
V = 0V
C E
V
I =
R + R
|
January 2004 ENGI 242/ELEC 222 32
Emitter Stabilized Bias Circuit Example
ENGI 242/ELEC 222 January 2004
Fixed Bias 17
January 2004 ENGI 242/ELEC 222 33
Design of an Emitter Bias CE Amplifier
Where .1VCC VE .2VCC
And .4VCC VC .6VCC
January 2004 ENGI 242/ELEC 222 34
Emitter Bias with Dual Supply
ENGI 242/ELEC 222 January 2004
Fixed Bias 18
January 2004 ENGI 242/ELEC 222 35
Emitter Bias with Dual Supply
Input Output