You are on page 1of 5

Practica 8

Divisores de frecuencia

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity divi151 is
Port (reloj : in STD_LOGIC;
clk : out STD_LOGIC);
end divi151;
architecture Behavioral of divi151 is
Begin
process (reloj)
variable cuenta: std_logic_vector(27 downto 0):=X"0000000";
begin
if rising_edge (reloj) then --hay un flanco de subida?
if cuenta=X"48009E0" then -- si cuenta es igual a 75500000?
cuenta:=X"0000000"; --entonces cuenta es igual 0
else --si no
cuenta:=cuenta+1; --cuenta= cuenta +1
end if;
end if;
clk <= cuenta(26); --sacamos sobre "clk" el valor del bit 26
end process;
end Behavioral;

Divisor de Frecuencias 1.51 seg


y Dc 11%

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY divi1seg IS
PORT (

Clk50Mhz: IN STD_LOGIC;

Clk: OUT STD_LOGIC );


END divi1seg;
ARCHITECTURE Div OF divi1seg IS
CONSTANT max: INTEGER := 50000000;
CONSTANT half: INTEGER := max/2;
SIGNAL count: INTEGER RANGE 0 TO max;

BEGIN
PROCESS
BEGIN
WAIT UNTIL Clk50Mhz'EVENT and Clk50Mhz = '1';
IF count < max THEN count <= count + 1;
ELSE count <= 0;
END IF;
IF count < half THEN Clk <= '0';
ELSE Clk <= '1';
END IF;
END PROCESS;
END Div;

Divisor de frecuencias
a 1 seg y Dc 50%

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity clk200Hz is
Generic ( limite : integer := 124999);
Port ( entrada: in STD_LOGIC;
reset : in STD_LOGIC;
salida : out STD_LOGIC );
end clk200Hz;

architecture Behavioral of clk200Hz is


signal contador: integer range 0 to limite := 0;
begin
divisor_frecuencia: process (reset, entrada)
variable temporal: STD_LOGIC;
begin
if (reset = '1') then
temporal := '0';
contador <= 0;
elsif rising_edge(entrada) then
if (contador = limite) then
temporal := NOT(temporal);
contador <= 0;
else
contador <= contador+1;
end if;
end if;
salida <= temporal;
end process;
end Behavioral;

Divisor de frecuencia a
200HZ y DC 50%

Practica 8

Construir un divisor de
frecuencias variable para
ciclos de trabajo:
25%
50%
75%
88%

y una frecuencia de 3
Segundos, cargarla en las
tarjeta Spartan

You might also like