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Lab Volt 32 Bit Microprocessor Instructors Guide
Lab Volt 32 Bit Microprocessor Instructors Guide
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3091577100307
by
Instructors Guide
Edition 2 91577-10
SECOND EDITION
All rights reserved. No part of this publication may be reproduced, stored in a retrieval system,
or transmitted in any form by any means, electronic, mechanical, photocopied, recorded, or
otherwise, without prior written permission from Lab-Volt Systems, Inc.
Information in this document is subject to change without notice and does not represent a
commitment on the part of Lab-Volt Systems, Inc. The Lab-Volt F.A.C.E.T. software and
other materials described in this document are furnished under a license agreement or a
nondisclosure agreement. The software may be used or copied only in accordance with the terms
of the agreement.
ISBN 0-86657-239-2
THIS
Table of Contents
Section 1 Workstation Inventory and Installation............................................................... 1-1
Inventory of Workstation ........................................................................................................ 1-1
Minimum Computer Requirements.................................................................................... 1-1
Equipment and Supplies..................................................................................................... 1-1
Equipment Installation ............................................................................................................ 1-1
Software Installation ............................................................................................................... 1-1
Section 2 Introduction to FACET Curriculum .................................................................... 2-1
Getting Started ........................................................................................................................ 2-2
Screen Buttons ........................................................................................................................ 2-3
FACET Help Screens and Resources...................................................................................... 2-4
Internet Access ........................................................................................................................ 2-5
Instructor Annotation Tool...................................................................................................... 2-5
Student Journal........................................................................................................................ 2-5
Assessing Progress .................................................................................................................. 2-6
Real-Number Questions and Answers .................................................................................... 2-8
Recall Values in Text ............................................................................................................ 2-10
Safety .................................................................................................................................... 2-10
Safety .................................................................................................................................... 2-11
Section 3 Courseware ............................................................................................................. 3-1
Unit 1 Trainer Familiarization .............................................................................................. 3-1
Exercise 1 Introduction to the Trainer ................................................................................. 3-4
Exercise 2 Operating the Trainer ....................................................................................... 3-12
Unit 2 Bus Operations .......................................................................................................... 3-21
Exercise 1 Bus States ......................................................................................................... 3-24
Exercise 2 32-Bit Bus Transfers ........................................................................................ 3-30
Exercise 3 Read and Write Cycles ..................................................................................... 3-37
Exercise CPU Initialization................................................................................................ 3-42
Unit 3 Memory Interfacing .................................................................................................. 3-51
Exercise 1 Memory Control Signals .................................................................................. 3-54
Exercise 2 Memory Address Decoding.............................................................................. 3-64
Exercise 3 Memory Data Transfers.................................................................................... 3-73
ii
Introduction
This Instructor Guide is divided into three sections and the appendices. It provides a unit-by-unit
outline of the Fault Assisted Circuits for Electronics Training (FACET) curriculum.
Section 1 Workstation Inventory and Installation contains a list and description of
equipment and materials required for all units in this course of study as well as installation
instructions.
Section 2 Introduction to FACET Curriculum provides a description of the courseware
structure, instructions on getting started with the multimedia presentation, and an explanation of
student-progress assessment methods.
Section 3 Courseware includes information that enables the instructor to gain a general
understanding of the units within the course.
Appendices include the questions and answers to the Pretest and Posttest plus additional specific
information on faults and circuit modifications (CMs).
Please complete and return the OWNER REGISTRATION CARD included with the CDROM. This will assist Lab-Volt in ensuring that our customers receive maximum support.
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THIS
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THIS
32 Bit Microprocessor
Description
F.A.C.E.T. base unit
Multimeter
Oscilloscope, dual trace
32-BIT MICROPROCESSOR circuit board
Student Workbook
Instructor Guide
MICROPROCESSOR APPLICATION BOARD (optional)
Equipment Installation
To install the hardware, refer to the Tech-Lab (minimum version 6.x) Installation Guide..
Software Installation
Third Party Application Installation
All applications and files that the courseware launches, or that are required for the course should
be installed before the courseware. Load all third party software according to the manufacturers'
directions. Install this software to the default location and note that location. (Alternatively, you
can install this software to a different location that you designate.) Remember to register all
software as required.
No third-party software is required for this course.
Installation of Courseware and Resources
To install the courseware and resources, refer to the Tech-Lab (minimum version 6.x) and
Gradepoint 2020 (minimum version 6.x) Installation Guide.
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Getting Started
Desktop
After the Tech-Lab System is installed, the TechLab icon appears on the desktop.
1. Click on the TechLab icon.
2. The student clicks on LOGON and selects his or her name.
3. The student enters his or her password and clicks on OK. (If he or she is creating a password,
four alphanumeric characters must be entered. The system will ask for the password to be
entered again for verification. Keep a record of the students' passwords.)
4. The previous two steps are repeated until all members of the student team have logged on.
Click on Complete and then Yes.
5. When the Available Courses menu appears, students click on the course name.
6. A window with the name of the course and a list of units for that course appears. Students
click on the unit name. The unit title page appears and the students are ready to begin.
Selecting Other Courses and Exiting the Courseware
1. Clicking on Exit when in a unit returns the student to the list of units for that course.
2. If students wish to select another unit, they click on it.
3. If students wish to exit FACET, they click on the X symbol in the upper right corner.
4. If students wish to exit another course, they click on the Course Menu button. The Available
Courses menu screen appears. They may also exit FACET from this screen by clicking on the
LOGOFF button.
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Screen Buttons
If you click on the FACET logo on the top right of the unit title page the About screen appears. It
acknowledges the copyright holder(s) of video and/or screen-capture material used in the topic.
The Menu button calls these menus:
when on an exercise menu screen, it calls the Unit Menu.
when on an exercise screen, it calls the Exercise Menu.
when on a unit screen, it calls the Unit Menu.
The Bookmark button marks the current screen. A student can click on the button at any time in
the lesson. The second time the student clicks on the button, the page displayed when the button
was first clicked will return to the screen. Any bookmarks used during a lesson are not saved
when the student logs out of the lesson.
The Application Launch button opens third-party software.
Click on the Resources button to view a pop-up menu. The pop-up menu includes access to a
calculator, a student journal, new terms and words, a print current screen option, the Lab-Volt
authored Internet Website, and a variety of FACET help screens.
The Help button aids students with system information. On certain screens the Help button
appears to be depressed. On these screens, clicking on the Help button will access Screen Help
windows (context-sensitive help).
The Internet button opens an Internet browser. Students will have unrestricted access to all
search engines and web sites unless the school administration has restricted this usage.
Use the Exit button to exit the course.
The right arrow button moves you forward to the next screen.
The left arrow button moves you backward to the previous screen.
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Internet Access
There are two ways for students to access the Internet:
The Internet button opens an Internet browser. Students have unrestricted access to all search
engines and websites unless the school administration has restricted this usage.
The Resources button pops up a menu that includes access to the Lab-Volt
authored Internet website. If students wish to access this site when they are not in
the lesson, then they must go to http://learning.labvolt.com.
NOTE: The Lab-Volt Internet site does not have content-filtering
software to block access to objectionable or inappropriate
websites.
Student Journal
The student journal is an online notebook that each student can access while they are logged into
TechLab. The journal allows students to share notes with other students in their workgroups.
When used in conjunction with GradePoint 2020, the instructor may post messages, review, edit,
or delete any journal note.
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Assessing Progress
Assessment Tools
Student assessment is achieved in several ways:
Exercise questions
Unit tests
Pretest and Posttest
Troubleshooting questions
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The computer
saves this input
value so that it can
be recalled for use
in later questions.
The answer to the question posed in the illustration above does not involve a recall value from a
previous question. It appears in the Instructor Guide (IG) as shown in the box below.
The information in the IG tells you where the question is located and the range of acceptable
answers. In this case, the acceptable answers fall within the range of the nominal answer plus or
minus 5 percent tolerance: (15 5%).
e1p1 stands for
Exercise 1 Procedure screen 1
Location: Exercise Procedure page:
se1p1, Question ID: e1p1a
VS =
Vdc
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A second example (shown below) illustrates an answer that the computer grades using a value
recalled from a previous question.
When a real-number question is based on a recall value from a previous question, the Min/Max
Value shown in the Instructor Guide is based upon a calculation using the lowest and highest
possible recall value. It represents the theoretical range of answers that could be accepted by the
computer. (It is not the nominal answer plus or minus the tolerance.)
To find the actual range of answers that the computer will accept onscreen, you must use the
actual recall value (14.5 in this example) in your calculations; see below.
Location: Exercise Procedure page:
se1p5, Question ID: e1p5c
IT =
mA
14.5/1650*1000 25% or
8.79 25% or
6.59 to 10.99
This calculated range is different from the
Min/Max Value shown in the IG, which
was based upon a calculation using the
lowest and highest possible recall value.
NOTE: After four incorrect answers, students will be prompted to press <Ins> to insert the
correct answer if this feature has been enabled in the configuration settings. When the question is
based on a value recalled from a previous question, answers obtained using the Insert key may
not match the nominal answers in this guide.
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The value of 10
was recalled
from a previous
screen.
The Instructor Guide lists the recall label in place of a number in this question.
This is a
recall label
for a value
recorded in a
previous
question.
The correct
answer will
depend on the
value the student
recorded in the
previous question.
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Safety
Safety is everyones responsibility. All must cooperate to create the safest possible working
environment. Students must be reminded of the potential for harm, given common sense safety
rules, and instructed to follow the electrical safety rules.
Any environment can be hazardous when it is unfamiliar. The FACET computer-based
laboratory may be a new environment to some students. Instruct students in the proper use of the
FACET equipment and explain what behavior is expected of them in this laboratory. It is up to
the instructor to provide the necessary introduction to the learning environment and the
equipment. This task will prevent injury to both student and equipment.
The voltage and current used in the FACET Computer-Based Laboratory are, in themselves,
harmless to the normal, healthy person. However, an electrical shock coming as a surprise will
be uncomfortable and may cause a reaction that could create injury. The students should be made
aware of the following electrical safety rules.
1. Turn off the power before working on a circuit.
2. Always confirm that the circuit is wired correctly before turning on the power. If required,
have your instructor check your circuit wiring.
3. Perform the experiments as you are instructed: do not deviate from the documentation.
4. Never touch live wires with your bare hands or with tools.
5. Always hold test leads by their insulated areas.
6. Be aware that some components can become very hot during operation. (However, this is not
a normal condition for your F.A.C.E.T. course equipment.) Always allow time for the
components to cool before proceeding to touch or remove them from the circuit.
7. Do not work without supervision. Be sure someone is nearby to shut off the power and
provide first aid in case of an accident.
8. Remove power cords by the plug, not by pulling on the cord. Check for cracked or broken
insulation on the cord.
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SECTION 3 COURSEWARE
SECTION 3 COURSEWARE
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32 Bit Microprocessor
UNIT OBJECTIVE
Locate and describe the various components on your circuit board, and demonstrate basic trainer
functions.
UNIT FUNDAMENTALS
Location: Unit Fundamentals page: sf3, Question ID: f3a
What other system components can communicate with the CPU in your computer via I/O
devices?
a. printer
b. mouse
c. disk drive
d. all of the above.
Location: Unit Fundamentals page: sf5, Question ID: f5a
maximum # =
Recall Label for this Question: None
Nominal Answer: 65536.0
Min/Max Value: (65536) to (65536)
Value Calculation: 65536.000
Correct Tolerance Percent = true
Correct Minus Tolerance = 0
Correct Plus Tolerance = 0
Location: Unit Fundamentals page: sf7, Question ID: f7a
Which of these is an input device?
a. keypad
b. LCD display
c. LEDs
CMS AVAILABLE
None
FAULTS AVAILABLE
None
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EQUIPMENT REQUIRED
F.A.C.E.T. base unit
Multimeter
Oscilloscope, dual trace
32-BIT MICROPROCESSOR circuit board
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REVIEW QUESTIONS
Location: Review Questions page: se1r1, Question ID: e1r1
1. What step(s) must you perform to start up the 32-BIT MICROPROCESSOR circuit board?
a. Set the control switches to their correct initial conditions.
b. Make sure the CPU is in the run mode.
c. Set some of shunts to their correct initial conditions.
d. All of the above.
Location: Review Questions page: se1r2, Question ID: e1r2
2. What type of waveform is indicated by the logic probe LEDs?
a. high level
b. low level
c. repeating high pulse
d. repeating low pulse
Location: Review Questions page: se1r3, Question ID: e1r3
3. In which circuit block can you monitor the signal INTRA?
a. IR CONTROLLER
b. CPU
c. PARALLEL PORT
d. SERIAL PORT
Location: Review Questions page: se1r4, Question ID: e1r4
4. When the CPU starts up in the run mode, you cannot read the address and data LEDs because
a. the wrong information is displayed.
b. the information is constantly changing.
c. the STEP switch has not been pressed.
d. the LEDs are turned off.
Location: Review Questions page: se1r5, Question ID: e1r5
5. Which circuit block synchronizes control signals between the CPU and its support circuitry?
a. DAC
b. ADC
c. BUS CONTROL
d. PARALLEL PORT
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CMS AVAILABLE
None
FAULTS AVAILABLE
None
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EXERCISE PROCEDURE
Location: Exercise Procedure page: se2p2, Question ID: e2p2a
2. Press <READ>. What message appears in the LCD display?
a. Lab-Volt 32 bit Proc. Trainer
b. Read Address?
c. Goto Address?
Location: Exercise Procedure page: se2p3, Question ID: e2p3a
The display shows the address as 04000 instead of 00004000 because you entered a
a. logical address and the display shows a physical address.
b. physical address and the display shows a logical address.
Location: Exercise Procedure page: se2p4, Question ID: e2p4a
The 11 appears in the first byte position. The second byte did not change because
a. you can enter only one byte at a time by using the WRT key.
b. RESET must be pressed before another byte is entered.
Location: Exercise Procedure page: se2p5, Question ID: e2p5a
What happens when you enter the last digit?
a. All the bytes you entered are shown in the display.
b. The display shows eight different bytes beginning at address 04008.
Location: Exercise Procedure page: se2p5, Question ID: e2p5c
5. Which key is more efficient to use if you need to enter a long program?
a. AUTO
b. WRT
Location: Exercise Procedure page: se2p10, Question ID: e2p10a
What instruction byte is located at address FFC14?
a. A3
b. 04
c. 50
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REVIEW QUESTIONS
Location: Review Questions page: se2r1, Question ID: e2r1
1. Which key(s) can you use to enter data into memory?
a. WRT
b. AUTO
c. Both of the above.
d. None of the above.
Location: Review Questions page: se2r2, Question ID: e2r2
2. Which register pair always contains the address of the next instruction that the CPU will
fetch?
a. A-B
b. C-D
c. SI-DI
d. CS-IP
Location: Review Questions page: se2r3, Question ID: e2r3
3. Press <REG> and select <(A-B)>. What number does EAX contain?
a. 33333333H
b. CCCCCCCCH
c. 00000000H
d. FFFFFFFFH
Location: Review Questions page: se2r4, Question ID: e2r4
4. Each time you press the FFWD key, the first byte in the display (after the address) represents
a. the first byte of the next instruction.
b. the contents of the CS-IP registers.
c. every eighth byte in the program listing.
d. None of the above.
Location: Review Questions page: se2r5, Question ID: e2r5
5. Which key would not be used to change the contents of a CPU register?
a. REG
b. FWD
c. WRT
d. STEP
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CMS AVAILABLE
CM 2
FAULTS AVAILABLE
FAULT 1
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UNIT TEST
Location: Unit Test Question page: sut1, Question ID: ut1
Which of the following is not used to view memory addresses?
a. HIGH/LOW data LED switch
b. HIGH/LOW address LED switch
c. address LEDs
d. LCD display
Location: Unit Test Question page: sut2, Question ID: ut2
Which circuit block accepts an analog input?
a. SERIAL PORT
b. PARALLEL PORT
c. ADC
d. DAC
Location: Unit Test Question page: sut3, Question ID: ut3
The IR CONTROLLER circuit block manages the CPU's
a. internal registers.
b. internal ROM.
c. interrupt signals.
d. input rate.
Location: Unit Test Question page: sut4, Question ID: ut4
Which circuit block(s) can contain memory devices?
a. RAM
b. USER ROM
c. MONITOR ROM
d. All of the above.
Location: Unit Test Question page: sut5, Question ID: ut5
What indication would appear on the logic probe LEDs each time you press the STEP switch?
a. constant high level
b. constant low level
c. constant pulsing
d. single pulse
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UNIT OBJECTIVE
Understand the basic data transfer operations of the 80386 microprocessor.
UNIT FUNDAMENTALS
Location: Unit Fundamentals page: sf1, Question ID: f1a
Which bus is bidirectional?
a. data bus
b. address bus
Location: Unit Fundamentals page: sf2, Question ID: f2a
First, the CPU activates the address bus. What information appears on the address lines?
a. data to be read
b. data to be written
c. the location for which data is to be written or read
Location: Unit Fundamentals page: sf3, Question ID: f3a
The CPU then looks for a response from the external device. According to the flow diagram,
what does the CPU do if a response is not received?
a. proceeds to the next step
b. waits for a response
Location: Unit Fundamentals page: sf3, Question ID: f3c
What is the direction of data flow for a read cycle?
a. from the CPU to an external device.
b. from an external device to the CPU.
Location: Unit Fundamentals page: sf5, Question ID: f3a
Instructions from memory are continuously transferred to the CPU. Each transfer requires a
a. read cycle.
b. write cycle.
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CMS AVAILABLE
None
FAULTS AVAILABLE
None
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EXERCISE PROCEDURE
Location: Exercise Procedure page: se1p2, Question ID: e1p2a
2. Does the message shown appear in the circuit board's Liquid Crystal Display (LCD)?
a. yes
b. no
Location: Exercise Procedure page: se1p5, Question ID: e1p5a
8. Does the prompt shown appear in the LCD?
a. yes
b. no
Location: Exercise Procedure page: se1p6, Question ID: e1p6a
11. Does the data shown appear in the LCD?
a. yes
b. no
Location: Exercise Procedure page: se1p7, Question ID: e1p7a
15. Each transition of the ADS# waveform coincides with a clock transition because
a. CLK is synchronized to ADS#.
b. ADS# is synchronized to CLK.
Location: Exercise Procedure page: se1p10, Question ID: e1p10a
The falling edge of ADS# was chosen to trigger the oscilloscope because it
a. occurs at the beginning of a bus cycle.
b. is synchronized to CLK.
c. represents the external device's response.
Location: Exercise Procedure page: se1p11, Question ID: e1p11a
17. Which part of the waveforms indicates the beginning of a bus cycle?
a. a high pulse on ADS#
b. a low pulse on RDY#
c. a low pulse on ADS#
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REVIEW QUESTIONS
Location: Review Questions page: se1r1, Question ID: e1r1
1. What can you use to identify all the types of CPU bus states (T1, T2, Ti, or wait)?
a. address and data bus information
b. ADS# and RDY#
c. ADS# only
d. RDY# only
Location: Review Questions page: se1r2, Question ID: e1r2
2. You can cause additional wait states to be added to each bus cycle by pressing <CM> to
toggle CM 12 on and off. How many total wait states are in the first bus cycle when CM 12 is
on?
a. 1
b. 2
c. 3
d. 4
Location: Review Questions page: se1r3, Question ID: e1r3
3. Which area highlighted on the state diagram represents a CPU wait state?
a. A
b. B
c. C
d. None of the above.
Location: Review Questions page: se1r4, Question ID: e1r4
4. Which step in the flow diagram corresponds to the activation of ADS#?
a. Send Address
b. Send Read Signal
c. Signal Address Valid
d. External Device Response
Location: Review Questions page: se1r5, Question ID: e1r5
5. Every bus cycle begins when ADS# goes low and ends
a. when ADS# goes high.
b. when RDY# is low at the end of a T2 state.
c. after the next T2 state.
d. after the next wait state.
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CMS AVAILABLE
CM 12 TOGGLE
FAULTS AVAILABLE
None
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EXERCISE PROCEDURE
Location: Exercise Procedure page: se2p2, Question ID: e2p2a
2. Does the prompt shown appear in the LCD?
a. yes
b. no
Location: Exercise Procedure page: se2p4, Question ID: e2p4a
6. To verify your data, press RESET, and then press <READ>. Enter address "0000:5000", and
verify that the data is 66 C7 06 00 70 FF FF FF. Press <FFWD> to view the second field, and
verify that the first line reads FF EB F5. Is all the data correct?
a. yes
b. no
Location: Exercise Procedure page: se2p8, Question ID: e2p8a
If the microprocessor were to transfer data from memory area 5000H to memory area 7000H,
which address bit would change?
a. A12
b. A13
c. A14
d. A15
Location: Exercise Procedure page: se2p10, Question ID: e2p10a
What do the falling edges of ADS# represent?
a. the end of a bus cycle
b. the beginning of a bus cycle
Location: Exercise Procedure page: se2p10, Question ID: e2p10c
What can you conclude from the waveforms?
a. Bus cycles occur only when A13 is low.
b. No data is transferred while A13 is high.
c. One bus cycle occurs while A13 is high.
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EXERCISE PROCEDURE
Location: Exercise Procedure page: se3p3, Question ID: e3p3a
Does the LCD appear as shown?
a. yes
b. no
Location: Exercise Procedure page: se3p6, Question ID: e3p6a
Do your waveforms appear as shown here?
a. yes
b. no
Location: Exercise Procedure page: se3p6, Question ID: e3p6c
The CPU is writing data for
a. one bus cycle.
b. five bus cycles.
Location: Exercise Procedure page: se3p8, Question ID: e3p8a
The ADS# and W/R# signals are shown in a different color for timing reference only. Do the
M/IO# and D/C# waveforms appear on your scope as shown here?
a. yes
b. no
Location: Exercise Procedure page: se3p8, Question ID: e3p8c
Which section consists of I/O data read cycles?
a. B
b. C
Location: Exercise Procedure page: se3p8, Question ID: e3p8e
What cycle type is executed in section B?
a. memory code read
b. memory data read
c. memory data write
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REVIEW QUESTIONS
Location: Review Questions page: se4r1, Question ID: e4r1
1. What is the first thing the 80386 microprocessor does after a reset?
a. writes to the display
b. writes an instruction to address FFFF FFF0H
c. fetches an instruction from address FFFF FFF0H
d. fetches an instruction from address 0000 0000H
Location: Review Questions page: se4r2, Question ID: e4r2
2. In the PROCEDURE, you confirmed that the logic levels in the table exist during the CPU's
reset state. What type of bus cycle is defined by these levels?
a. memory code read
b. memory data read
c. I/O data read
d. I/O code read
Location: Review Questions page: se4r3, Question ID: e4r3
3. What function is not performed by the circuit shown?
a. synchronizing a reset signal with the CPU CLK
b. power-up reset
c. pushbutton reset
d. external reset
Location: Review Questions page: se4r4, Question ID: e4r4
4. During a power-up reset, the RES signal goes low
a. when C40 charges up to the inverter's input threshold voltage.
b. when C40 discharges completely.
c. immediately when power is applied.
d. None of the above.
Location: Review Questions page: se4r5, Question ID: e4r5
5. When you close S5 and press S7, this circuit causes the CPU to execute single cycles by
a. disabling the PLDRDY# signal.
b. resetting the CPU.
c. generating one PLDRDY# pulse each time S7 is pressed.
d. generating one ADS# pulse each time S7 is pressed.
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CMS AVAILABLE
None
FAULTS AVAILABLE
None
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UNIT TEST
Location: Unit Test Question page: sut1, Question ID: ut1
Where does the information that the CPU writes to or reads from an external device appear?
a. on the address bus
b. on the data bus
c. at the status outputs
d. at the control inputs
Location: Unit Test Question page: sut2, Question ID: ut2
Which group of signals does the CPU use to select the location for data to be transferred?
a. address bus
b. data bus
c. status outputs
d. control inputs
Location: Unit Test Question page: sut3, Question ID: ut3
Any cycle that begins with a low pulse on ADS# and ends with a low pulse on RDY# is a
a. clock cycle.
b. read cycle only.
c. write cycle only.
d. bus cycle.
Location: Unit Test Question page: sut4, Question ID: ut4
What size group of bits can be involved in an aligned transfer?
a. byte
b. word
c. doubleword
d. All of the above.
Location: Unit Test Question page: sut5, Question ID: ut5
An aligned transfer is faster than a misaligned transfer because an aligned transfer requires
a. two bus cycles.
b. one bus cycle.
c. more data.
d. less data.
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UNIT OBJECTIVE
Demonstrate memory transfers and describe the functions of memory control signals.
UNIT FUNDAMENTALS
Location: Unit Fundamentals page: sf3, Question ID: f3a
In which type of memory is it better to store the monitor program for the 32-BIT
MICROPROCESSOR circuit board?
a. RAM
b. ROM
Location: Unit Fundamentals page: sf4, Question ID: f4a
The CPU enables a single chip or group of chips at a time so that
a. only one location in one chip or group is selected.
b. one location in every chip or group is selected.
Location: Unit Fundamentals page: sf5, Question ID: f5a
When A13 is high,
a. RAM 1 is selected.
b. RAM 2 is selected.
c. both RAMs are selected.
Location: Unit Fundamentals page: sf6, Question ID: f5a
How many RAMs could be selected if 3 address lines (A13, A14, and A15) were decoded?
a. 6.
b. 8.
c. 16.
Location: Unit Fundamentals page: sf9, Question ID: f5a
What other signal is common to both the bus controller and the address decoder?
a. W/R#.
b. M/IO#.
c. D/C#.
d. None of the above.
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32 Bit Microprocessor
CMS AVAILABLE
None
FAULTS AVAILABLE
None
3-52
32 Bit Microprocessor
3-53
32 Bit Microprocessor
3-54
32 Bit Microprocessor
3-55
32 Bit Microprocessor
3-56
32 Bit Microprocessor
3-57
32 Bit Microprocessor
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32 Bit Microprocessor
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32 Bit Microprocessor
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32 Bit Microprocessor
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EXERCISE PROCEDURE
Location: Exercise Procedure page: se2p2, Question ID: e2p2a
In this circuit, the BS16# output will be active for
a. RAM transfers.
b. ROM transfers.
c. Both of the above.
Location: Exercise Procedure page: se2p4, Question ID: e2p4a
4. Adjust the scope TIME VARIABLE control so that two cycles of W/R# occupy exactly 10
horizontal divisions. Does the scope trace appear as shown?
a. yes
b. no
Location: Exercise Procedure page: se2p6, Question ID: e2p6a
Do the RAMSEL# and MROMSEL# signals on your scope match this figure?
a. yes
b. no
Location: Exercise Procedure page: se2p7, Question ID: e2p7a
During horizontal interval 4, the CPU is
a. reading from RAM.
b. reading from the monitor ROM.
c. writing to RAM.
Location: Exercise Procedure page: se2p8, Question ID: e2p8a
During which interval does the CPU write to RAM?
a. 2
b. 3
c. 5
d. 6
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REVIEW QUESTIONS
Location: Review Questions page: se2r1, Question ID: e2r1
1. An address decoder decodes
a. part of the CPU address bus.
b. all of the CPU address bus.
c. part of the CPU data bus.
d. part of the CPU data and address buses.
Location: Review Questions page: se2r2, Question ID: e2r2
2. If 4 address bits were decoded, how many memory blocks could be selected?
a. 4
b. 8
c. 16
d. 32
Location: Review Questions page: se2r3, Question ID: e2r3
3. Which conditions of A17 and A18 are always necessary for BS16# to be active?
a. 1
X
b. 1
0
c. 1
1
d. 0
0
Location: Review Questions page: se2r4, Question ID: e2r4
4. The data you wrote to 0000H also appears at 10000H because
a. 10000H is an image of 00000H.
b. A17 is shorted to ground.
c. A18 is shorted to ground.
d. None of the above.
Location: Review Questions page: se2r5, Question ID: e2r5
Which of these addresses is also an image of 0000H?
a. 80000H
b. 90000H
c. Both of the above.
d. None of the above.
3-71
32 Bit Microprocessor
CMS AVAILABLE
CM 13
FAULTS AVAILABLE
None
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32 Bit Microprocessor
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(MSB)
byte 2 byte 3
EA
02
01
00
00
01
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REVIEW QUESTIONS
Location: Review Questions page: se3r1, Question ID: e3r1
1. 32-bit RAM transfers in your circuit are more efficient than 16-bit ROM transfers because
a. ROM is read-only memory.
b. RAM has more memory.
c. RAM transfers require fewer bus cycles to accomplish the same task.
d. All of the above.
Location: Review Questions page: se3r2, Question ID: e3r2
2. How many cycles were needed to fetch the first jump instruction in the 32-bit RAM and 16-bit
ROM programs you executed in the PROCEDURE?
RAM
a. 5
b. 2
c. 3
d. 1
ROM
5
3
2
1
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32 Bit Microprocessor
CMS AVAILABLE
None
FAULTS AVAILABLE
None
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32 Bit Microprocessor
UNIT TEST
Location: Unit Test Question page: sut1, Question ID: ut1
You can determine the size of each location in a memory device by the number of
a. address lines.
b. data lines.
c. control lines.
d. All of the above.
Location: Unit Test Question page: sut2, Question ID: ut2
Which chip select input(s) must be active to enable this RAM IC?
a. CS1 only
b. CS2 only
c. both CS1 and CS2
d. either CS1 or CS2
Location: Unit Test Question page: sut3, Question ID: ut3
If the highlighted control signals are low and all others are high, what type of cycle is executed?
a. write bytes 0 and 1 to RAM
b. write bytes 2 and 3 to RAM
c. read bytes 0 and 1 from RAM
d. None of the above.
Location: Unit Test Question page: sut4, Question ID: ut4
Which control input to PLD U23 is not necessary for the operation of the address decoder?
a. ADS#
b. M/IO#
c. CLK
d. All are necessary.
Location: Unit Test Question page: sut5, Question ID: ut5
The address decoder's BS16# output activates when which block select is active?
a. RAMSEL#
b. MROMSEL#
c. UROMSEL#
d. Either b. or c.
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UNIT OBJECTIVE
Demonstrate the signals needed to transfer data between the 386 CPU by using the 32-BIT
MICROPROCESSOR circuit board and its associated input/output components.
UNIT FUNDAMENTALS
Location: Unit Fundamentals Page: sf6, Question ID: f6a
What is the address range for the digital-to-analog converter?
a. 00 to 0FH
b. 10 to 1FH
c. 20 to 2FH
CMS AVAILABLE
None
FAULTS AVAILABLE
None
NEW TERMS AND WORDS
unipolar - having one polarity.
bipolar - having two polarities.
retriggerable one-shot - a monostable multivibrator that can be triggered during its pulse time to
prevent time-out.
EQUIPMENT REQUIRED
F.A.C.E.T. base unit
Multimeter
Oscilloscope, dual trace
32-BIT MICROPROCESSOR circuit board
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REVIEW QUESTIONS
Location: Review Questions Page: se1r1, Question ID: e1r1
1. Data lines D16 thru D23 represent which byte of the 4-byte data bus?
a. byte 0
b. byte 1
c. byte 2
d. byte 3
Location: Review Questions Page: se1r2, Question ID: e1r2
2. When the ADC is in the bipolar mode, what is the input voltage range?
a. +10V to 10V
b. +5V to 5V
c. 0V to +10V
d. 0V to 10V
Location: Review Questions Page: se1r3, Question ID: e1r3
3. The DAC is set to the 10V range and has a resolution of 0.039V. What is the output voltage
when a 10H is written to the DAC?
a. 0.62V
b. 5V
c. 10V
d. 0.39V
Location: Review Questions Page: se1r4, Question ID: e1r4
4. Before the ADC is read, what signal must be applied to the ADC?
a. DAC_EN#
b. ADC_EN#
c. ADC_CV
d. DR#
Location: Review Questions Page: se1r5, Question ID: e1r5
5. When the DAC is set to the 2.56V range, a change of 1 LSB on the input causes how much of
a voltage change on the output?
a. 0.010V
b. 0.256V
c. 0.100V
d. 0.0256V
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32 Bit Microprocessor
CMS AVAILABLE
None
FAULTS AVAILABLE
None
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32 Bit Microprocessor
3-88
32 Bit Microprocessor
EXERCISE PROCEDURE
Location: Exercise Procedure Page: se2p1, Question ID: e2p1a
What must the state of the input signals be to activate the PPI_EN#?
a. high
b. low
Location: Exercise Procedure Page: se2p5, Question ID: e2p5a
The PPI chip is selected when the signal is
a. low.
b. high.
Location: Exercise Procedure Page: se2p6, Question ID: e2p6a
What state must address line A4 be in to generate the PPI_EN# signal?
a. low
b. high
Location: Exercise Procedure Page: se2p7, Question ID: e2p7a
What state must address line A5 be in to generate the PPI_EN# signal?
a. low
b. high
Location: Exercise Procedure Page: se2p8, Question ID: e2p8a
What state must address line A6 be in to generate the PPI_EN# signal?
a. low
b. high
Location: Exercise Procedure Page: se2p9, Question ID: e2p9a
What state of the M/IO# signal is required to generate the PPI_EN# signal?
a. low
b. high
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REVIEW QUESTIONS
Location: Review Questions Page: se2r1, Question ID: e2r1
1. The PPI_EN# signal must be enabled to
a. write to the display.
b. read the keypad.
c. output data to the DAC.
d. input data from the ADC.
Location: Review Questions Page: se2r2, Question ID: e2r2
2. The key code generated by a pressed key is read on which port?
a. PPI PA
b. PPI PB
c. PPI PC
d. None of the above.
Location: Review Questions Page: se2r3, Question ID: e2r3
3. The PPI PB port is used as a(n)
a. serial port.
b. keypad interface.
c. parallel port.
d. analog output port.
Location: Review Questions Page: se2r4, Question ID: e2r4
4. Which signal is generated when one-shot U40 times out?
a. DAC_EN#
b. PPI_EN#
c. KSCLK
d. STROBE
Location: Review Questions Page: se2r5, Question ID: e2r5
5. The CPU reads DIP switch S3 during the intitialization routine by reading the PPI
a. PA port.
b. PB port.
c. PC port.
d. None of the above.
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32 Bit Microprocessor
CMS AVAILABLE
CM 2
FAULTS AVAILABLE
None
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32 Bit Microprocessor
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32 Bit Microprocessor
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REVIEW QUESTIONS
Location: Review Questions Page: se3r1, Question ID: e3r1
1. What is the address range of the DP_EN signal?
a. 30H to 3FH
b. 40H to 4FH
c. 50H to 5FH
d. 60H to 6FH
Location: Review Questions Page: se3r2, Question ID: e3r2
2. What address is used to write a character to the display?
a. 51H
b. 55H
c. 50H
d. 52H
Location: Review Questions Page: se3r3, Question ID: e3r3
3. What is the level for an RS-232C logic 1?
a. 5V to 15V
b. 0V
c. 5V
d. +5V to +15V
Location: Review Questions Page: se3r4, Question ID: e3r4
4. The serial port is used to
a. transmit serial data.
b. receive serial data.
c. transmit and receive serial data.
d. transmit and receive parallel data.
Location: Review Questions Page: se3r5, Question ID: e3r5
5. The display on the 32-BIT MICROPROCESSOR circuit board is a (an)
a. LED display.
b. fluorescent display.
c. incandescent display.
d. LCD display.
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CMS AVAILABLE
None
FAULTS AVAILABLE
None
3-99
32 Bit Microprocessor
UNIT TEST
Location: Unit Test Page: sut1, Question ID: ut1
A DAC port is connected as shown. From what map is the DAC port addressed?
a. memory
b. I/O
c. ROM
d. RAM
Location: Unit Test Page: sut2, Question ID: ut2
The address range of the DAC_EN# signal is 20H to 2FH. What address is used to write to the
DAC?
a. 20H
b. 21H
c. 22H
d. 23H
Location: Unit Test Page: sut3, Question ID: ut3
To output data from the CPU to an I/O device, what instruction must be used?
a. JMP
b. OUT
c. IN
d. MOV
Location: Unit Test Page: sut4, Question ID: ut4
Which of the following devices is used to input analog information into a microprocessor
system?
a. ADC
b. DAC
c. serial port
d. PPI
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32 Bit Microprocessor
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32 Bit Microprocessor
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UNIT OBJECTIVE
Demonstrate how the 80386 CPU processes hardware and software interrupts. Verify results by
entering and analyzing test programs on the 32-BIT MICROPROCESSOR circuit board and by
observing signals with the oscilloscope and logic probe.
UNIT FUNDAMENTALS
Location: Unit Fundamentals page: sf5, Question ID: f5a
In this figure, the stack pointer decrements by 2, indicating that data is stored in
a. bytes.
b. words.
c. doublewords.
Location: Unit Fundamentals page: sf6, Question ID: f6a
Is the data that you pop from the stack always the first or last data pushed onto the stack?
a. last
b. first
Location: Unit Fundamentals page: sf8, Question ID: f8a
At the end of the service routine, the CPU pops the information off the stack in
a. the order in which it was pushed.
b. reverse order.
Location: Unit Fundamentals page: sf11, Question ID: f8a
The maskable interrupts are masked when
a. IF is set.
b. IF is cleared.
Location: Unit Fundamentals page: sf13, Question ID: f8a
Which type generates an interrupt after the instruction that causes the exception?
a. fault.
b. trap.
c. abort.
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EQUIPMENT REQUIRED
F.A.C.E.T. base unit
Oscilloscope, dual trace
32-BIT MICROPROCESSOR circuit board
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32 Bit Microprocessor
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EXERCISE PROCEDURE
Location: Exercise Procedure page: se1p3, Question ID: e1p3a
The vector 0000:7000 points the CPU to the NMI service routine. Where must the vector be
located?
a. 00002H
b. 00004H
c. 00008H
Location: Exercise Procedure page: se1p4, Question ID: e1p4a
In this PROCEDURE section, you will establish 02000H as the first stack location to which the
CPU will store register information. How can you establish 02000H as the top of the stack?
a. Change the CS/IP register contents to 0000:2000.
b. Change the SS/SP register contents to 0000:2000.
c. Write the SS/SP register contents to 0000:2000.
Location: Exercise Procedure page: se1p4, Question ID: e1p4c
When an interrupt occurs, what register contents are pushed onto the stack?
a. flags
b. code segment
c. instruction pointer
d. All of the above.
Location: Exercise Procedure page: se1p5, Question ID: e1p5a
4. View the contents of the BP/FL registers. What number is currently contained in the flags
register?
a. 0002H
b. 00000000H
Location: Exercise Procedure page: se1p5, Question ID: e1p5c
What is the status of the interrupt enable flag?
a. set
b. cleared
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REVIEW QUESTIONS
Location: Review Questions page: se1r1, Question ID: e1r1
1. When a non-maskable interrupt occurs, the CPU uses a vector type number
a. from anywhere in the range 00-FFH.
b. that is part of the interrupt instruction.
c. that is taken from the stack.
d. of 02.
Location: Review Questions page: se1r2, Question ID: e1r2
2. Which register's contents are not automatically pushed onto the stack when an interrupt
occurs?
a. code segment
b. instruction pointer
c. stack pointer
d. flags register
Location: Review Questions page: se1r3, Question ID: e1r3
3. How can you determine the address at which the NMI vector is located?
a. Multiply the type number by 4.
b. Divide the type number by 4.
c. The type number is the address.
d. None of the above.
Location: Review Questions page: se1r4, Question ID: e1r4
4. Suppose the stack segment and stack pointer registers contain the address 0000:2006 before an
interrupt occurs. Assume that the service routine itself does not perform any stack operations.
What address is contained in SS/SP when the CPU returns from the service routine?
a. 0000:2000
b. 0000:2003
c. 0000:2006
d. cannot be determined
Location: Review Questions page: se1r5, Question ID: e1r5
5. How can you disable a non-maskable interrupt?
a. by setting the IF bit in the FLG register
b. by clearing the IF bit
c. with an instruction
d. None of the above.
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CMS AVAILABLE
None
FAULTS AVAILABLE
None
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32 Bit Microprocessor
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32 Bit Microprocessor
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32 Bit Microprocessor
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32 Bit Microprocessor
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REVIEW QUESTIONS
Location: Review Questions page: se2r1, Question ID: e2r1
1. You can disable the CPU's recognition of maskable interrupts by
a. setting the IF bit in the flags register.
b. clearing the IF bit in the flags register.
c. changing command word ICW1.
d. changing command word ICW2.
Location: Review Questions page: se2r2, Question ID: e2r2
2. The complete interrupt acknowledge sequence for maskable interrupts consists of
a. two INTA cycles and then four idle states.
b. four idle states and then two INTA cycles.
c. one INTA cycle, four idle states, and then a second INTA cycle.
d. one INTA cycle and then four idle states.
Location: Review Questions page: se2r3, Question ID: e2r3
3. When a maskable interrupt occurs, the vector type number
a. is sent to the CPU by the PIC.
b. is sent to the PIC by the interrupting device.
c. can be anywhere in the range 00-FFH.
d. is always 02H.
Location: Review Questions page: se2r4, Question ID: e2r4
4. If the CPU sends the PIC a value of A8H for ICW2, what is the hex type number for IR2?
a. A8H
b. AAH
c. ABH
d. ACH
Location: Review Questions page: se2r5, Question ID: e2r5
5. Which PIC control signal is not used when the CPU sends command words?
a. CS
b. WR
c. A0
d. INTR
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CMS AVAILABLE
CM 18
FAULTS AVAILABLE
None
3-123
32 Bit Microprocessor
Exercise 3 Exceptions
EXERCISE OBJECTIVE
Explain and demonstrate how exceptions interrupt the 80386 microprocessor.
EXERCISE DISCUSSION
Location: Exercise Discussion page: se3d2, Question ID: e3d2a
The INT3 software interrupt, also called a breakpoint, has a type number of 3. At what address
is the ISR's vector located?
a. 00003H
b. 00012H
c. 0000CH
Location: Exercise Discussion page: se3d7, Question ID: e3d7a
Which addition results in an overflow?
a. 7EH + 01H
b. 7FH + 01H
c. Both of these.
Location: Exercise Discussion page: se3d9, Question ID: e3d9a
What interrupt is specified by the op code CD 10? (Remember that the type numbers in the table
are in decimal and the op code bytes are in hexadecimal.)
a. invalid task state segment
b. coprocessor error
c. debug exception
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EXERCISE PROCEDURE
Location: Exercise Procedure page: se3p2, Question ID: e3p2a
At what address can you find the interrupt vector for INTO?
a. 00004H
b. 00010H
c. 00016H
Location: Exercise Procedure page: se3p2, Question ID: e3p2c
What is the address of the INT3 interrupt vector?
a. 00003H
b. 0000CH
c. 00012H
Location: Exercise Procedure page: se3p4, Question ID: e3p4a
The location's segment is contained in the data segment (DS) register. The first two lines set DS
to 0000H. What is the complete jump-to address?
a. 0000:0010
b. 0010:0000H
Location: Exercise Procedure page: se3p6, Question ID: e3p6a
Which message appears in the LCD display?
a. A
b. B
c. C
Location: Exercise Procedure page: se3p6, Question ID: e3p6c
3. Press any key on the keypad. The error message is
a. still displayed.
b. gone.
Location: Exercise Procedure page: se3p8, Question ID: e3p8a
The flow diagram in the help window (click on Help) illustrates the operation of the main
program and the service routines. For what condition is an error message displayed?
a. overflow
b. no overflow
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UNIT TEST
Location: Unit Test Question page: sut1, Question ID: ut1
The 80386 CPU recognizes an external maskable interrupt
a. any time the CPU receives an INTR signal.
b. only when a software interrupt instruction is executed.
c. only when the OF flag is set.
d. only when the IF flag is set.
Location: Unit Test Question page: sut2, Question ID: ut2
When a return instruction occurs at the end of a service routine, the CPU executes the next
instruction
a. at the beginning of the service routine.
b. at the beginning of the program.
c. after the point at which the interrupt occurred.
d. at the top of the stack.
Location: Unit Test Question page: sut3, Question ID: ut3
What type of interrupts are handled by the PIC?
a. exceptions
b. external maskable
c. external non-maskable
d. both b and c
Location: Unit Test Question page: sut4, Question ID: ut4
What information is transferred on the data bus between the CPU and the PIC for processing
maskable interrupts?
a. PIC programming information
b. vector type numbers
c. Both of the above.
d. None of the above.
Location: Unit Test Question page: sut5, Question ID: ut5
How can you generate a non-maskable interrupt to the CPU?
a. Activate the NMI# input.
b. Press the PB HALT switch.
c. Insert an INT 02 instruction into a program.
d. All of the above.
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UNIT OBJECTIVE
Describe and execute the eleven addressing modes of the 80386 CPU by using the 32-BIT
MICROPROCESSOR circuit board.
UNIT FUNDAMENTALS
Location: Unit Fundamentals page: sf3, Question ID: f3a
In the real mode, what is the maximum physical address size of external memory of the 80386
CPU?
a. 32 Kbytes (215)
b. 4 Gbytes (232)
c. 1 Mbyte (220)
Location: Unit Fundamentals page: sf7, Question ID: f7a
In the real mode, what is the size of a data segement?
a. 64 Kbytes (216)
b. 4 Gbytes (232 bytes)
Location: Unit Fundamentals page: sf9, Question ID: f9a
What is the function of registers within the 80386 CPU?
a. Registers provide very fast access to data in RAM.
b. Registers store data within the CPU and control the behavior of the processor.
c. Registers perform fast arithmetic calculations.
CMS AVAILABLE
None
FAULTS AVAILABLE
None
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EXERCISE PROCEDURE
Location: Exercise Procedure page: se2p6, Question ID: e2p6a
2. Read the AX register. Does it contain the memory operand 83C5?
a. yes
b. no
Location: Exercise Procedure page: se2p7, Question ID: e2p7a
4. What is the displacement value used to calculate the EA?
a. 83C5
b. 3070
Location: Exercise Procedure page: se2p7, Question ID: e2p7c
5. What is the EA?
a. 3070
b. 0100
Location: Exercise Procedure page: se2p8, Question ID: e2p8a
6. What is the logical address of the memory operand?
a. 0200:1000
b. 0100:3070
Location: Exercise Procedure page: se2p9, Question ID: e2p9a
9. Read the AX register. Was the memory operand 83C5 moved into the AX register?
a. yes
b. no
Location: Exercise Procedure page: se2p9, Question ID: e2p9c
10. The instruction used what type of memory operand addressing mode?
a. direct
b. based
c. register indirect
Location: Exercise Procedure page: se2p15, Question ID: e2p15a
12. Read the AX register, does it contain the memory operand A3DC?
a. yes
b. no
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REVIEW QUESTIONS
Location: Review Questions page: se2r1, Question ID: e2r1
1. For 16-bit and 32-bit addressing, what value(s) can you use to compose an effective address
(EA)?
a. code and data segment selector values
b. instruction pointer and code segment selector values
c. segment selector and offset values
d. displacement, base, and index values
Location: Review Questions page: se2r2, Question ID: e2r2
2. For 32-bit addressing, the base value is in what register(s)?
a. BX or BP
b. any 32-bit general purpose register except ESP
c. any 32-bit general purpose register
d. SI or DI
Location: Review Questions page: se2r3, Question ID: e2r3
3. When the base value is in the BP register, what is the default segment for data?
a. SS
b. DS
c. CS
d. FS
Location: Review Questions page: se2r4, Question ID: e2r4
4. The instruction MOV AX, DS:3070H uses what type of addressing mode?
a. register indirect
b. direct
c. based
d. index
Location: Review Questions page: se2r5, Question ID: e2r5
5. The instruction MOV EDX, [DI+BX+0030H] uses what type of addressing mode?
a. based index
b. register indirect
c. based index with displacement
d. index
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CMS AVAILABLE
None
FAULTS AVAILABLE
None
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UNIT TEST
Location: Unit Test Question page: sut1, Question ID: ut1
What determines the physical address of the next instruction for the 80386 CPU?
a. the data segment's base address and the EA
b. the code segment's base address and the offset in the IP register
c. the addressing mode specified in the instruction code
d. the data in the EFLAGS register
Location: Unit Test Question page: sut2, Question ID: ut2
What is the function of the six segment registers?
a. They contain data that specifies the six active segments in memory.
b. They contain the next six instruction codes.
c. They contain the results of arithmetic and logical operations.
d. The segment registers control operations and indicate the status of the 80386 CPU.
Location: Unit Test Question page: sut3, Question ID: ut3
Where can an operand be located?
a. in an instruction
b. in memory
c. in a general purpose register
d. All of the above.
Location: Unit Test Question page: sut4, Question ID: ut4
What is the purpose of the 80386 CPU addressing modes?
a. They specify the op code field of the instruction.
b. They determine the address size of the segments.
c. They specify the destination of the operand.
d. They locate an operand.
Location: Unit Test Question page: sut5, Question ID: ut5
When the 80386 CPU operates in the real mode, what must the address size be?
a. 8 bits or 16 bits
b. 16 bits
c. 32 bits
d. 16 bits or 32 bits
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UNIT OBJECTIVE
Write instructions for the 80386 CPU with machine codes and use the instructions in memory
test programs that runs by using the 32-BIT MICROPROCESSOR circuit board.
UNIT FUNDAMENTALS
Location: Unit Fundamentals page: sf7, Question ID: f7a
During one bus cycle, the 80386 CPU can fetch how many bytes of an instruction code?
a. 8 bytes
b. 4 bytes
c. 2 bytes
Location: Unit Fundamentals page: sf8, Question ID: f8a
At what address does the above memory test program use a register indirect memory addressing
mode MOV instruction?
a. 04000
b. 04002
c. 04004
d. 0400B
CMS AVAILABLE
None
FAULTS AVAILABLE
None
NEW TERMS AND WORDS
machine language - a language that can be used directly by a microprocessor; a binary
language; also called object code.
EQUIPMENT REQUIRED
F.A.C.E.T. base unit
32-BIT MICROPROCESSOR circuit board
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EXERCISE PROCEDURE
Location: Exercise Procedure page: se1p4, Question ID: e1p4a
For the instruction MOV CX,12ABH, what format is used?
a. IMMED TO MEM
b. IMMED TO REG
c. MEM TO ACCUM
Location: Exercise Procedure page: se1p5, Question ID: e1p5a
The format for the MOV CX,12ABH instruction is shown. What fields are included in the MOV
CX,12ABH instruction? (Click on <?> to view the general instruction code format fields for the
80386 CPU.)
a. op code and displacement
b. operand size prefix, op code, and mod r/m
c. op code and immediate
d. op code, mod r/m, and immediate
Location: Exercise Procedure page: se1p7, Question ID: e1p7a
1. The hex code for the instruction MOV CX,12ABH will contain how many bytes?
a. 2
b. 3
c. 4
Location: Exercise Procedure page: se1p7, Question ID: e1p7c
2. What is the binary code of the first nibble (4 bits)?
a. 1101
b. 1011
c. cannot be determined
Location: Exercise Procedure page: se1p7, Question ID: e1p7e
3. What is the hex code for the first nibble (4 bits)?
a. 8
b. C
c. B
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EXERCISE PROCEDURE
Location: Exercise Procedure page: se4p6, Question ID: e4p6a
5. Press <STEP> to execute the first instruction, MOV DL,00. Read the DL register. Was hex 00
moved to the DL register?
a. yes
b. no
Location: Exercise Procedure page: se4p6, Question ID: e4p6c
6. Press <EXIT>, and then press <STEP> to execute the second instruction, MOV BX,SI. Read
the BX register. Was the starting offset value 6000 moved to the BX register?
a. yes
b. no
Location: Exercise Procedure page: se4p7, Question ID: e4p7a
7. Press <EXIT>, and then press <STEP> to execute the third instruction, MOV [BX],DL. This
instruction moves the contents of the DL register (00) to memory address 06000. Read address
06000. Was hex 00 moved to address 06000?
a. yes
b. no
Location: Exercise Procedure page: se4p7, Question ID: e4p7c
8. Press <STEP> to execute the fourth instruction, INC BX. This instruction increments (INC)
the contents of the BX register by hex 01 from (6000 to 6001). Read the BX register. Was the
BX register incremented to 6001?
a. yes
b. no
Location: Exercise Procedure page: se4p8, Question ID: e4p8a
8. At what address will the program be after you press <STEP> two times to execute CMP
BX,DI and JLE 4004H?
a. 0400B
b. 04004
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REVIEW QUESTIONS
Location: Review Questions page: se4r1, Question ID: e4r1
1. What occurs during the first loop between addresses 04004 and 04009 within the memory test
program?
a. Each address is tested for hex 00.
b. The program writes hex 00 to the addresses to be tested.
c. The program loads the SI and DI registers with the starting and ending addresses, respectively.
d. All of the above.
Location: Review Questions page: se4r2, Question ID: e4r2
2. The SI register contains 7500, the DI register contains 7AFF, the DS register contains 0000,
and the CS register contains 4000. What address range is tested?
a. 00000 to 07500
b. 04000 to 07AFF
c. 00000 to 04000
d. 07500 to 07AFF
Location: Review Questions page: se4r3, Question ID: e4r3
3. What does the instruction CMP DL,[BX] at address 0400D cause the CPU to do?
a. compare the data in a memory address (offset in the BX register) with the test data in the
DL register
b. compare the values in the BX and DL registers
c. copy the value in the BX register to the DL register
d. write the data in a memory address (offset in the BX register) to the DL register
Location: Review Questions page: se4r4, Question ID: e4r4
4. What does the instruction JNZ 400BH at address 0401A cause the CPU to do?
a. move to the next instruction if the value in the DL register is not hex 00
b. cause a jump to address 0400B if the value in the DL register is hex 00
c. cause a jump to address 0400B if the value in the DL register is not hex 00
d. reset the data in address 0400B to hex 00
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UNIT TEST
Location: Unit Test Question page: sut1, Question ID: ut1
The general instruction format for the 80386 CPU contains 9 possible fields. What field always
appears in the instruction code?
a. op code
b. mod r/m
c. s-i-b
d. displacement
Location: Unit Test Question page: sut2, Question ID: ut2
In the real mode, the above instruction requires which hexadecimal prefix? The operand is in the
data segment.
a. 66
b. 67
c. 2E
d. 26
Location: Unit Test Question page: sut3, Question ID: ut3
What does the d bit determine?
a. the operand size
b. whether the r/m field specifies a register or memory location
c. whether the reg field specifies the source or the destination register
d. if an s-i-b byte is necessary
Location: Unit Test Question page: sut4, Question ID: ut4
What are the mod bits for the above instruction?
a. 00
b. 01
c. 10
d. 11
Location: Unit Test Question page: sut5, Question ID: ut5
If the operand is in memory, what do the r/m bits specify?
a. the destination operand
b. how the CPU calculates the effective address
c. the source operand
d. the register
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Unit 8 Troubleshooting
UNIT 8 TROUBLESHOOTING
TROUBLESHOOTING
Location: Troubleshooting page: ttrba1, Question ID: trba1a
Does the performance check indicate that the circuit is working properly?
a. yes
b. no
Location: Troubleshooting page: ttrba2, Question ID: trba2
The fault is
a. CLK shorted to ground.
b. A1 shorted to A2.
c. MROMSEL# shorted to VCC.
d. W/R# open.
Location: Troubleshooting page: ttrbb1, Question ID: trbb1a
Does the performance check indicate that the circuit is working properly?
a. yes
b. no
Location: Troubleshooting page: ttrbb2, Question ID: trbb2
The fault is
a. ADS# shorted to VCC.
b. ADS# open.
c. RDY# shorted to VCC.
d. RDY# shorted to ground.
Location: Troubleshooting page: ttrbc1, Question ID: trbc1a
Does the performance check indicate that the circuit is working properly?
a. yes
b. no
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Unit 8 Troubleshooting
CMS AVAILABLE
None
FAULTS AVAILABLE
Fault 1
Fault 2
Fault 3
Fault 5
Fault 8
Fault 10
Fault 11
Fault 12
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EXERCISE PROCEDURE
Location: Exercise Procedure page: se2p6, Question ID: e2p6a
Besides PB7, how many other outputs from port B perform a function on the application board?
a. one
b. two
c. three
d. all
Location: Exercise Procedure page: se2p7, Question ID: e2p7a
The maximum speed of the motor is about 30 rps. How many pulses per second does the optical
interrupter output at maximum motor speed?
pps =
Recall Label for this Question: pps
Nominal Answer: 150.0
Min/Max Value: (150) to (150)
Value Calculation: 150.000
Correct Tolerance Percent = true
Correct Minus Tolerance = 0
Correct Plus Tolerance = 0
Location: Exercise Procedure page: se2p9, Question ID: e2p9a
9. Record the frequency of the resulting waveform.
f=
Hz
Recall Label for this Question: f1
Nominal Answer: 150.0
Min/Max VALUE: (120) to (180)
Value Calculation: 150.000
Correct Tolerance Percent = true
Correct Minus Tolerance = 20
Correct Plus Tolerance = 20
Location: Exercise Procedure page: se2p9, Question ID: e2p9c
Is your measured frequency of # f1 # Hz close to your calculated value of 150 pulses per second?
a. yes
b. no
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NOTE: Min/Max Values shown are based upon a calculation using the absolute
lowest and highest recall value. By using the actual input in your calculations, you
will determine the correct value.
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a.
b.
c.
d.
on-time
08H
08H
80H
80H
off-time
08H
80H
08H
80H
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EXERCISE PROCEDURE
Location: Exercise Procedure page: se3p6, Question ID: e3p6a
What type of temperature control is accomplished by this program?
a. open-loop
b. closed-loop
Location: Exercise Procedure page: se3p7, Question ID: e3p7a
9. Measure the DACOUT voltage.
DACOUT =
V
Recall Label for this Question: None
Nominal Answer: 10.0
Min/Max Value: (9.5) to (10.5)
Value Calculation: 10.000
Correct Tolerance Percent = true
Correct Minus Tolerance = 5
Correct Plus Tolerance = 5
Location: Exercise Procedure page: se3p8, Question ID: e3p8a
11. Measure the voltage at ADCIN.
ADCIN =
Vdc
Recall Label for this Question: vr
Nominal Answer: 5.0
Min/Max Value: (4.5) to (5.5)
Value Calculation: 5.000
Correct Tolerance Percent = true
Correct Minus Tolerance = 10
Correct Plus Tolerance = 10
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NOTE: Min/Max Values shown are based upon a calculation using the absolute lowest and
highest recall value. By using the actual input in your calculations, you will determine the correct
value.
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NOTE: Min/Max Values shown are based upon a calculation using the absolute lowest and
highest recall value. By using the actual input in your calculations, you will determine the correct
value.
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UNIT TEST
Location: Unit Test Question page: sut1, Question ID: ut1
A microprocessor drives a dc motor with a square wave having a 50% duty cycle. How can the
CPU increase motor speed?
a. Increase the square wave's off-time.
b. Increase the square wave's on-time.
c. Decrease the square wave's on-time.
d. Increase the square wave's frequency.
Location: Unit Test Question page: sut2, Question ID: ut2
What hex value could be written to the DAC to apply about +1.5V to the motor? (Note: Use the
digital DAC value in the equation.)
a. 20H
b. 40H
c. C0H
d. E0H
Location: Unit Test Question page: sut3, Question ID: ut3
What is the function of the optical interrupter in the microprocessor motor control circuit shown?
a. feed back speed information to the microprocessor
b. feed back direction information to the microprocessor
c. regulate the motor speed
d. All of the above.
Location: Unit Test Question page: sut4, Question ID: ut4
In linear motor control, a microprocessor controls speed by
a. switching the motor on and off.
b. varying the duty cycle of a square wave applied to the motor.
c. reversing the polarity of the voltage applied to the motor.
d. applying an analog voltage to the motor.
Location: Unit Test Question page: sut5, Question ID: ut5
In the motor controller circuit shown in the help window (press Help), the DACOUT signal from
the microprocessor board has a 0-10V range. Op amp U5A converts the range to 3V to +3V for
what purpose?
a. to expand the range
b. to increase DAC resolution
c. to control maximum voltage and direction
d. All of the above.
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heater
off
on
off
on
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14. Which group of signals does the CPU use to select the location for data to be transferred?
a. address bus
b. data bus
c. status outputs
d. control outputs
15. Which of the following would you not find on a ROM IC?
a. bidirectional data lines.
b. chip enable input.
c. output enable input.
d. address inputs.
16. Random-Access Memory (RAM) is also called
a. read-write memory.
b. read-only memory.
c. write-only memory.
d. None of the above.
17. What size group of bits can be involved in an 80386 aligned transfer?
a. byte.
b. word.
c. doubleword.
d. all of the above.
18. If 4 address bits were decoded by an address decoder, how many memory blocks could be
selected?
a. 4
b. 8
c. 16
d. 32
19. You can determine the size of each location in a memory device by the number of
a. data lines.
b. address lines.
c. control lines.
d. all of the above
20. An 80386 aligned transfer is faster than a misaligned transfer because an aligned transfer
requires
a. more data.
b. less data.
c. two bus cycles.
d. one bus cycle.
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35. When an interrupt occurs, the 80386 CPU saves its place in the main program by
a. popping the CS, IP, and FLG register contents from the stack.
b. pushing the CS, IP, and FLG register contents to the stack.
c. jumping to an interrupt service routine.
d. saving status information in a register.
36. How can you determine the address at which the 80386 NMI vector is located?
a. The type of number is the same as the address.
b. Divide the type number by 4.
c. Multiply the type number by 4.
d. none of the above.
37. What is a memory segment?
a. the contents of one of the segment registers.
b. the location in memory for the next instruction.
c. the data stored in the general-purpose registers.
d. an independent region in memory space that can be assigned a specific type of data.
38. Where are the 80386 instruction pointer, segment, general-purpose, and flags registers
located?
a. in the CPU
b. it depends on the application program
c. in RAM.
d. The instruction pointer, general-purpose, and flags registers are in the CPU, and the
segment register is in RAM.
39. For 16-bit and 32-bit addressing, what values can the 80836 use to compose an effective
address (EA)?
a. code and data segment selector values
b. displacement, base, and index values
c. segment selector and offset values
d. instruction pointer and code segment selector values
40. For 32-bit addressing, the base value is in what 80386 register(s)?
a. any 32-bit general purpose register.
b. any 32-bit general purpose register except ESP.
c. BX or BP.
d. SI or DI.
41. Which 80386 addressing mode can be used only for 32-bit addressing?
a. based index with displacement.
b. based index.
c. register indirect.
d. based scaled index.
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49. When an 80386 addressing mode uses a scale factor, how many bits must be in the address?
a. 8
b. 16
c. 32
d. any of the above
50. What does the 80386 instruction JNZ 400BH cause the CPU to do?
a. move to the next instruction if the value in the DL register is not 00H.
b. cause a jump to address 0400B if the ZF flag bit is not 0.
c. cause a jump to address 0400B if the value in the DL register is 00H.
d. reset the data in address 0400B to 00H.
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FAULT
ACTION
SCHEMATIC
SWITCH NO.
S21
S22
S23
S25
S28
30
10
31
11
32
12
18
18
12
12
13
13
14
14
15
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Semiconductor Fundamentals
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Semiconductor Fundamentals
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best results, and to avoid confusion, we prefer that you write with a description of the problem.
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C-2
THIS
THIS
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32-Bit Microprocessor
Instructor Guide
32-Bit Microprocessor
Instructor Guide
32-Bit Microprocessor
Instructor Guide