Dr.

Abhijit RAsati
EEEDepartment,
BITS,Pilani

Impact of scaling
((1)) Test Complexity
p
y
(2) Power dissipation

Wafer sort or probe test:

Some testing is done during device fabrication to assess the
integrity of the process itself
differentiates ppotentially
y ggood die from defective ones
The wafer is scribed and cut, and the potentially good dies
are packaged

Test
site
i characterization:
h
i i
These
h
are designed
d i d to characterize
h
i
the processing technology through measurement of parameters
such as
Gate threshold
Poly-silicon
y
field threshold
Metal field threshold
Poly and metal sheet resistances
Contact resistance etc.

In general, each chip is subjected to two types of tests:

(1) Parametric Tests.
Tests
DC parametric tests include: These tests measure steadystate electrical characteristics usingg Ohms law
Shorts test
Opens test
Maximum
i
current test
Leakage test
Output short current test
Output drive current test
Threshold levels test

AC parametric tests:
Chip delays caused by input and output capacitances:
Rise and fall time test
Propagation
p g
delayy test
Setup and hold test
Functional speed test
Access
A
time
i test
Refresh and pause time test

Functional Tests.
They check for proper operation of a verified design by
testing the internal chip nodes
e.g.
g stuck type
yp faults
Often, functional vectors are understood as verification
vectors

However,
i the
in
h ATE
A
world,
ld these
h
are functional
f
i l fault
f l
coverage vectors applied during manufacturing test.
These two types of functional tests may or may not
be the same.
Functional tests mayy be applied
pp
at an elevated
temperature to guarantee specifications.

Guard-Banding
Speed binning