In this lecture:

Lecture 11: Registers and counters

Dr Pete Sedcole
Department of Electrical & Electronic Engineering
Imperial College London
http://cas.ee.ic.ac.uk/~nps/

Registers and shift registers

Counters: synchronous and asynchronous

(Floyd 7.4, 8.1, 9.1)

(Tocci 5.17 5.19, 7.1, 7.19 7.20)

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Registers

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11.2

Example symbol and implementation

A register is a digital electronic circuit capable of storing several bits

of data
normally made from D flip-flops
normally bits are moved in and out all at once (i.e., in parallel)
must have a CLOCK input
can also have RESET (synchronous) or CLEAR (asynchronous)
inputs

CLEAR

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CLEAR

R
C1

CLOCK
D0

1D

Q0

D1

Q1

D2

Q2

11.3

The stored values

are present on the
register outputs
Q0, Q1, Q2
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R
C1

CLOCK
D0

D0

The values on inputs

D0, D1, D2, are
stored in the register
on the positive edge
of the CLOCK

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1D

Q0

1D

D1

Q1

D2

Q2

Q0

D1

1D
C1

C1

Q1

D2

1D

Q2

C1
R

CLOCK
CLEAR
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11.4

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Shift registers

Shift register operation

In a shift register, bits move along the register from one flip-flop to
the next flip-flop, like a queue
Many applications, for example:
Conversion of data between parallel format and bit-serial format
Random number generators
Construction:
Q0
Din

Q1

C1

Bits are input serially into Din

On the positive edge of the clock, each bit moves right by one flipflop
The data can be read at any time from the outputs Q[2:0]
Therefore 3 bits can be entered in serial and read out in parallel
format after 3 clock cycles

1D

C1

C1

Q2

1D

1D

CLOCK

Also note that all the flip-flops can be asynchronously reset

It is also possible to have versions where all flip-flops can be loaded
with data in parallel and read out in serial

CLEAR
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11.5

Q0
Din

1D
C1
R

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Q1
1D
C1
R

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11.6

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A pseudo-random number generator

Q2
1D
C1
R

Din

CLOCK

Q0
1D
C1

CLEAR

Q1

Q3

Q2
1D

1D

C1

C1

OUT

1D
C1
S

CLOCK

CLOCK

PRESET

CLEAR
Din

1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 1, 1, 0, 1, 0, 1, and then repeat

Q0
Q1

Q2
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A shift register where the input is a function of the state

The value of the OUT signal will be:

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A shift register of N-bits can be used to generate a pseudo-random

sequence of 2N-1 bits before repeating

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11.8

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Binary counters

Recall: frequency divider

Decimal Q2 Q1 Q0

CLOCK
Q0
Q1
Q2

A 3-bit binary counter

Note that in frequency:
Q0 is half CLOCK
Q1 is half Q0
Q2 is half Q1

1D

CLOCK1

C1

Q[2:0]
CLOCK

+
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Asynchronous binary counter

Q0

1D

Q
CLOCK

C1

Produces an output signal that is half the

frequency of the input clock signal

11.9

CLOCK2

CTR3

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1D

CLOCK1

Q1

1D

Q
C1

11.10

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Ripple counter operation

Q2

1D

Q0

1D

Q
CLOCK

C1

This counter is asynchronous: the flip-flops are not all clocked with
the same clock signal
This counter is also known as a ripple counter since changes
ripple from one end of the counter to the other
Can also be implemented with JK flip-flops

C1

Q1

1D

Q
C1

Q2

Q
C1

CLOCK
Q0
Q1
Q2

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Limitations of asynchronous ripple counters

It takes a small but non-zero amount of time for each flip-flop to

change state
typically the Clock-to-Q time is about 10ns
It takes time for the changes to ripple through the whole counter
for an n-bit counter, it would take ~ n x 10ns
for a 3-bit counter, this is 30ns
so the maximum clock frequency is 1/30ns = 33.3MHz

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Synchronous binary counters

All flip-flops are clocked with the same signal

therefore all outputs change simultaneously

The sequence of the count is controlled by combinational logic

this is sometimes called the state sequence
note that synchronous binary counters use both
sequential and combinational elements

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Example: 3-bit up-counter

000

001

010

011

100

101

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Implementation

110

Use a register of flip-flops and logical combinations of state variables

111

CLOCK

State diagram

Current state

From the state diagram, we can

construct the state transition table.
Here, label the state variables ABC,
where A is the MSB and C is the LSB

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11.15

Next state

A+

B+ C+

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Example using
D flip-flops:

combinational
circuit
?

C1

A+

1D

B+
C+

A
B
C

The design task is to create the combinational circuit

it needs to supply the next input A+, B+, C+, so that on the
next clock the correct sequence is followed
other flip-flops could be used, such as JK flip-flops
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11.16

19 November 2008