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Ghép nối và điều khiển hệ thống
Ghép nối và điều khiển hệ thống
TI LIU LU HNH NI B
LI NI U
MC LC
CHNG 1:
1.1.
ROM
V
X
L
ng dy d liu v a ch MVT
BGN
Bn phm
Mn hnh
BGN
My in
BGN
b nh
ngoi
BGN
Song song
/ni tip
cng
BGN
CD-ROM Song song
/ni tip
BGN
Vo/ra
BGN
Vo/ra
Cm bin
o lng
C cu
chp
hnh
ng dy
iu khin
Thit
b
CN
MVT
/Vi K
Hnh 1.1: Cu trc h GN trao i d liu tin gia MVT v TBNV
Trong : VXL l vit tt ca vi x l
RAM l random-access memory
ROM l read-only memory
BGN l b ghp ni
CD-ROM l compact disk read-only memory
CN l cng nghip
K l iu khin
Ging vin: Nguyn Vn Minh Tr
BGN
GN GN
logic cng
ngh
iu khin
TBNV
s liu
Trao i
d liu
Chng trnh
Chng trnh
Cha
TBNV sn sng ?
Ngt
Trao i
d liu
Ri
Trao i
d liu
a) ng b
b) Khng ng b
1.2.
Mch OR
- SN7432
Vcc 4B 4A 4Y 3B 3A 3Y
14 13 12 11 10 9 8
1 2 3
1A 1B 1Y
Mch NOT
- SN7404:
- SN7405
- SN7406
4 5 6 7
2A 2B 2Y GND
Vcc 6A 6Y 5A 5Y 4A 4Y
14 13 12 11 10 9 8
A
L
H
Y
H
L
1 2 3 4 5 6 7
1A 1Y 2A 2Y 3A 3Y GND
Mch EX-OR
- SN74136
Vcc 4B 4A 4Y 3B 3A 3Y
14 13 12 11 10 9 8
1 2 3 4 5 6 7
1A 1B 1Y 2A 2B 2Y GND
B
L
L
H
H
Y
L
H
H
L
10
Vcc 4B 4A 4Y 3B 3A 3Y
14 13 12 11 10 9 8
1 2 3 4 5 6 7
1A 1B 1Y 2A 2B 2Y GND
Mch NOR
- SN7402
- SN7428
A
L
H
L
H
B
L
L
H
H
Y
H
H
H
L
Vcc 4B 4A 4Y 3B 3A 3Y
14 13 12 11 10 9 8
1 2 3 4 5 6 7
1A 1B 1Y 2A 2B 2Y GND
Mch EX-NOR
- SN74HC266
A
L
H
L
H
B
L
L
H
H
Y
H
L
L
L
A
L
H
L
H
B
L
L
H
H
Y
H
L
L
H
1 2 3 4 5 6 7
1A 1B 1Y 2A 2B 2Y GND
A
X
L
H
Y
Z
L
H
1 2 3 4 5 6 7
1C 1A 1Y 2C 2A 2Y GND
11
SN74126
SN74426
3C 3A 3Y
Vcc 4C 4A 4Y 3B
14 13 12 11 10 9 8
C
L
H
H
A
X
L
H
Y
Z
L
H
1 2 3 4 5 6 7
1C 1A 1Y 2C 2A 2Y GND
2 2
CK PR 2Q 2 Q
14 13 12 11 10 9 8
CLR
Q
CK
D PR Q
D PR Q
CK
CLRQ
1 2 3 4 5 6 7
1 1Q 1 Q GND
1 1D 1
CLR
CK PR
PR
CLR
CK
L
H
L
H
H
H
H
L
L
H
H
H
X
X
X
X
X
X
H
L
X
H
L
H*
H
L
Q0
Q
L
H
H*
L
H
Q0
12
u vo
Thanh
ghi ni
u ra
OE
LE
Di
Q0
Q0
Kch hot v c
thanh ghi
Oi
u vo
OE
Kch hot v c
thanh ghi
CP
Thanh
ghi ni
Di
u ra
Oi
Q0
Q0
13
STB
X
H
H
Trong : H l logic 1
X l bt k
l sn xung m
H
L
L
L
X
L
H
X
DO
Z
L
H
Q0
L l logic 0
Z l trng thi tr khng cao
Q0 l cht gi tr ca d liu sau cng
14
H
x
x
L
L
L
L
L
L
L
L
x
H
x
L
L
L
L
L
L
L
L
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
L
x
x
L
H
H
H
H
H
H
H
H
x
x
x
L
L
L
L
H
H
H
H
x
x
x
L
L
H
H
L
L
H
H
x
x
x
L
H
L
H
L
H
L
H
H
H
H
L
H
H
H
H
H
H
H
Output
15
Cc chn A1A8, B1B8 l cc chn gi/ nhn d liu 2 hng tng ng.
Chn 19 ( G ) l chn chn IC (Chip Enable).
Chn 1 (DIR) l chn chn hng gi/ nhn d liu (Direction).
DIR
Hot ng
D liu vo B, ra A
D liu vo A, ra B
16
Cc lnh vo ra d liu
Instruction
Data
Width
Comment
IN AL,d8
IN AL,DX
IN AX,d8
16
IN AX,DX
16
OUT d8,AL
OUT DX,AL
OUT d8,AX
16
OUT DX,AX
16
17
Data
Width
Comment
outportb(addr_port,data_var)
Data_var=inportb(addr_port)
outport(addr_port,data_var)
16
Data_var=inportb(addr_port)
16
outp(addr_port,data_var)
Data_var=inp(addr_port)
outpw(addr_port,data_var)
16
Data_var=inp(addr_port)
16
Data
Width
Comment
Port[addr] := var1;
Var := port[addr];
V d:
Uses crt;
18
Chu k c
address
bus
data bus
D liu t
TBNV
D liu c
c vo VXL
Chu k ghi
D liu c
ghi ra TBNV
D liu t
VXL
RD
WR
Hnh 1.5: Gin thi gian tn hiu trn bus h thng.
Mi chu k bus (bus cycle) bao gm vic chuyn 1 t d liu gia VXL vi b nh hoc
TBNV. Mi chu k bus bt u khi VXL xut mt a ch chn mt v tr b nh hoc
cc cng vo ra. Trong gin ny, cc bus a ch v d liu c biu din bng 1 cp
ng thng ch thng tin trn bus n nh. Khi cc ng trn s ct ngang nhau
din t d liu thay i. ng nt t l trng thi th ni khi khng c thit b no
li n.
19
data1 = inport(addrport);
data1 := port(addrport);
Trnh bin dch s chuyn on lnh trn thnh m my, v khi chy on m my
ny, VXL s to ra cc tn hiu:
- A0A15 t addrport
- RD kch hot mc 0.
B gii m s so snh cc gi tr trn ng a ch vi a ch cng cho trc, nu
trng a ch, u ra b gii m s kch hot mc 0. Do u ra mch OR s mc 0,
kch hot cho b m ba trng thi m ra, v d liu t TBNV s vo bus d liu ca
VXL. Lc ny, VXL s nhn
- D0 ,..., D7 gn vo cho bin data1.
Kt thc chu k lnh, RD tr v mc 1.
a ch
A0A15
Gii m
RD
D0
BCB 1
D1
BCB 2
D7
Bus MVT
BCB 7
BGN
TBNV
20
+E
K/i
D0
D1
D7
Bus MVT
BGN
Hnh 2.2: Ca ra n gin, khng c i thoi
outportb(addrport,data2);
port(addrport) := data2;
Trnh bin dch s chuyn on lnh trn thnh m my, v khi chy on m my
ny, VXL s to ra cc tn hiu:
- A0A15 t addrport
- WR kch hot mc 0.
B gii m s so snh cc gi tr trn ng a ch vi a ch cng cho trc, nu
trng a ch, u ra b gii m s kch hot mc 0. Do u ra mch NOR s nhy
ln mc 1, kch hot cho b thanh ghi m m ra, v TBNV nhn d liu t MVT, gm:
- D0 ,..., D7 tng ng vi bin data2.
Kt thc chu k lnh, WR tr v mc 1.
21
Q0
Gii m
RD
Q1
Q D
CKLQ
Cl
Xung
np
D0
BCB 1
D1
BCB 2
D7
BCB 7
Bus MVT
TBNV
Hnh 2.3: Ca vo c i thoi
22
D Q
QCKL
TBNV sn
sng nhn
Pr
Gii m
WR
S liu sn
sng
1 DQ
QCKL
Cl
Q
Ghi nhn
K/i
D0
D1
D7
Bus MVT
BGN
TBNV
23
1
2
3
4
5
RD
6
CS
GND 7
A1 8
A0 9
PC7 10
PC6 11
PC5 12
PC4 13
PC0 14
PC1 15
PC2 16
PC3 17
PB0 18
PB1 19
PB2 20
8255A
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
Phn iu khin ni b
PA4
PA5
PA6
PA7
Bus s
liu
D0 ...D7 m
bus s
liu
RD
iu
WR
khin
A1
A0
c/ghi
RESET
CS
iu
khin
nhm
B
D0 D7 INTRA
INTRB
RD
D0 D7
RD
WR
RESET
VXL
INTR
iu
khin
nhm
A
WR
RESET
D0
D1
D2
D3
D4
D5
D6
D7
VCC
PB7
PB6
PB5
PB4
PB3
Phn GN vi TBNV
WR
RST
PA0 PA7
8255A
A0
A1
A0
A1
A2 An
Gii m
a ch
cao
CS
TBNV
PC0 PC7
PB0 PB7
24
Vi mch PPI 8255A l vi mch iu khin bng chng trnh c p dng kh rng
ri. Hnh 1.10 trnh by s ghp ni 8255A, gm c:
1. Phn ghp ni vi VXL:
- B m s liu trao i d liu hai chiu gia MVT v ng dy s liu
trong.
- B logic iu khin c vit: tc b gii m a ch lnh cho cc thanh ghi m v
thanh ghi iu khin.
Vi t hp cc tn hiu a ch (A0, A1). chn vi mch ( CS ), cc lnh c ( RD ) v
ghi ( WR ) ca VXL, ta c cc lnh ghi v c khc nhau cho cc ca (A, B, C) v t
iu khin (control word) nh bng 2.4.
Bng 2.4: Bng trng thi ca 8255A
A1
A0
CS
RD
WR
0
0
1
0
1
0
0
0
0
0
0
0
1
1
1
c ca A
c ca B
c ca C
1
0
0
1
1
1
0
1
0
1
0
0
0
0
0
0
1
1
1
1
1
0
0
0
0
Ghi ca A
Ghi ca B
Ghi ca C
Ghi thanh ghi iu khin
25
00 - Ch 0
01 - Ch 1
1x - Ch 2
Chiu ca A
1 - vo
0 - ra
Chiu ca C cao
1 - vo
0 - ra
Nhm B
Chiu ca C thp
1 - vo
0 - ra
Chiu ca B
1 - vo
0 - ra
Ch ca B
1 - Ch 1
0 - Ch 0
26
27
28
29
30
31
3. Ch 2
Ch hot ng ny cung cp kh nng trao i d liu vi cc thit b ngoi vi s
dng mt ng truyn 8 bit va truyn va nhn d liu (Bus vo/ra hai chiu). Cc
tn hiu hi thoi c dng trong ch ny iu khin vic truyn d liu cng
tng t nh ch 1.
Cc chc nng c bn ca ch 2:
Ging vin: Nguyn Vn Minh Tr
32
ACK (Acknowledge)
33
4. Ch kt hp
Ngoi vic hot ng ring r theo tng ch , 8255 cn c kh nng hot ng ng
thi kt hp cc ch khi khng phi tt c cc bit trong cng C c s dng iu
khin hoc dnh cho trng thi. Cc bit cn li c th c s dng thc hin cc chc
nng sau :
Khi c lp trnh l cc ng vo tn hiu
Tt c cc ng vo tn hiu u c th c truy cp trong sut qu trnh c cng
C thng thng. Nh trong hnh v minh ho sau :
34
35
36
Reset
RD
RD
WR
WR
A0
A0
A1
A1
A2 A19
PC5
PC1
Data strobe
Busy
My
in
D0 D7
D0 D7
VXL
PA0 PA7
Gii
m a
ch
CS
PC0
PC4
PB0 PB7
Busy
My
c
driver right
bng
37
D0 D7 PA0 PA7
D0 D7
INTRA
VXL INTR
PC3
INTA
Data strobe
PC4
PC6
8255
PC7
ACK
OBFA
My in
Reset
D0 D7
D0 D7
VXL
RD
RD
WR
WR
A0
A0
A1
A1
A2 A19
Gii
m a
ch
CS
PA0 PA7
D0 D7
DAC
PB0
Cht s liu
PB1
Cho php a ra
Li ra
tng t
ADC
PB2
PB3
Cht s liu
Li vo
tng t
D0 D7
38
Yes
Bt u
Bt u
My in bn?
No
a s liu ra
Yes
My c bn?
No
c s liu vo
Kt thc
Kt thc
39
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
1
0
0
0
1
data_C4 := 10h
data_C1 := 02h
data_C0 := 01h
40
sync
d liu
Thu
ng
b
- My thu ch trng thi ch, khi c k t ng b SYNC th my pht xung
nhp trong my thu bt ln v chuyn sang ch thu xung ng b c kch
hot bi k t SYNC.
Pht
Thu
ng
b
41
D liu truyn c th 5,6 ,7,8 bit; thng thng l 7 bit ( nu truyn s liu v ch ci)
hay 8 bit ( nu truyn c cc k t m rng iu khin ht File). Mt li tin gm:
- 1 bit Start thng l mc 0 (+12V). Theo chun RS232C, tn hiu t my tnh
qua cng Com, mc in p l 12 V v c qui nh:0=12V, 1= -12V.
- 58 bit d liu, y d liu truyn i l m ASCII, nh s 0 s c truyn
i l m ASCII = 48 = 030h ch khng phi l truyn i 0.
- 1 bit bc dng kim tra tnh chn l d liu truyn. Tng s bit 1 ca mt li
tin (k c bit chn l) s c ghi vo bit chn l v c kim tra so snh ni
pht v ni thu.
- 1, 1.5 hay 2 bit Stop (tu theo s la chn trc khi trao i) cng mc 1. S
bit Stop thc cht l di ca tn hiu Stop mc logic 1.
Bit Start dng ng b xung nhp my pht v my thu.
Nu khong cch gn di 300m, s thu pht l khng cn MODEM.
nhng khong cch ln ngi ta khng dng my pht xung ngoi m dng
MODEM to xung ng b cho c my pht v my thu. Vic dng MODEM l
chng nhiu trn ng truyn. Trn ng dy in thoi, ngi ta khng pht tng bit
0/1 m dng MODEM (modulation-demodulation) iu ch tn hiu thnh dng xoay
chiu (02400 Hz, 11200 Hz) v truyn tn hiu xoay chiu .
3.1.2 Mch trao i d liu ni tip.
1. Mch khng cn b ghp ni:
-s dng 2 chn ra-vo ni tip SID ( serial IN) v SOD ( serial OUT) ca vi x
l 8085 trao i.
-c th dng 1 chn ca li vo ra song song ca VXL lm chn vo ra ni
tip.
Trao i tin kiu ny khng phc to trong cu to mch nhng phc tp trong
qu trnh lp trnh v theo di thit b, i hi nhiu thi gian x l.
Thit b ngoi vo/ra song
song
VXL
SOD
SID
CLK
D
C
42
BGN c chc nng chuyn d liu song song t my tnh (h VXL) thnh tn hiu
dng ni tip v truyn n TBNV. truyn chnh xc, BGN ngoi chc nng
chuyn d liu song song thnh ni tip, n cn to ra cc bit Start, stop, parity
ng khung d liu. Loi ny lm vic n gin nhng khng m rng c thit
b ngoi vi, khong cch truyn tin ngn.
BGN
ss-nt
VXL
TBNV
(VXL)
nt
VXL
BGN
ss-nt
TBNV
(VXL)
ss
BGN
nt-ss
in thoi
RS-232C
ng dy
MODEM
BGN
ss-nt
MODEM
VXL
RS-232C
BGN
ss-nt
TBC
(VXL)
ss
43
44
45
(3F8)
(3FB)
(3F8)
(3F9)
(3FD)
(3F8)
(3FC)
(3FE)
(3F9)
(3FA)
DLAB
A2
A1
A0
c/ghi
Thanh ghi
46
0
0
1
1
x
x
x
x
x
x
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
c/ghi
c/ghi
c/ghi
c
c/ghi
c/ghi
c/ghi
c/ghi
c/ghi
Mi thanh ghi trong 8250 tng ng vi mt a ch cng, trong c hai thang ghi
c bit, n c chc nng c th thay th tu thuc gi tr bit DLAB (divitor latch access
bit Bit truy cp cht) (DLAB l bit D7 ca thanh ghi dng s liu).
Nu DLAB = 1 th thanh ghi thc hin chc nng cht chia phn cao v phn
thp.
Chc nng
D tr, lun t bng 0.
cho php 8250 pht yu cu ngt trng thi MODEM
47
cho php 8250 pht yu cu ngt theo trng thi dng truyn nhn hoc
ngt dng thng tin (li chn l, trn khung).
cho php 8250 pht yu cu ngt khi thanh ghi m pht rng.
cho php 8250 pht yu cu ngt khi thanh ghi m thu y, d liu
sn sng
d) Thanh ghi cht chia phn thp (Divisor Latch - LS) tng ng DLAB = 1, a ch
l 3F8h, hay 2F8h.
e) Thanh ghi cht chia phn cao (Divisor Latch MS) tng ng DLAB = 1, a ch
l 3F9h, hay 2F9h.
t tc truyn mong mun, gi tr tnh ton c t trong hai thanh ghi,
c gi l thanh ghi cht chia tc c tnh theo cng thc
Tn s nhp chun
B chia =
16 x tc baud mong mun
-
S chia
Baud
S chia
50
0900
1200
0060
110
0417
2400
0030
150
0300
4800
0018
300
0180
9600
000C
600
00C0
11520
0001
48
49
i) Thanh ghi trng thi dng (Line Status Register LSR) a ch 3FDh
Chc nng thanh ghi ny cho bit trng thi dng tn hiu trn ng dy
nh th no, cc bit D0D5 u c th gy ra ngt nu cc bit tng ng
trong thanh ghi IER c lp .
Cc bit trng thi c ngha nh sau:
Bit
Chc nng
50
D tr
=1: bo thanh ghi chuyn pht rng (Transmitter Shift Register Empty), bo mt
k t c pht i, bit ny b xo khi c mt k t chuyn t THR sang TSR.
=1: bo thanh ghi m truyn rng, k t chuyn t THR sang TSR (Transmitter
Shift Register), bit ny b xo khi CPU a k t n THR.
=1: bo nhn c tn hiu Break, bit ny b xo khi c thanh ghi LSR.
=1: bo li khung (framming error) chng hn bit stop =0, bit ny b xo khi
CPU c thanh ghi LSR.
=1: nhn bo c li kim tra chn l (parity error), bit ny b xo khi CPU c
thanh ghi LSR.
=1: c li trn (over run) xy ra khi k t trc b mt, bit ny b xo khi CPU
c thanh ghi LSR.
=1: nhn c 1 k t v n trong thanh ghi m thu (RBR), bit ny b
xo v 0 khi CPU c thanh ghi RBR.
j) Thanh ghi trng thi modem (MODEM Status Regisster MSR), a ch 3FEh
Thanh ghi ny cn c gi l thanh ghi trng thi vo t RS232C v n cho bit trng
thi hin thi ca cc tn hiu iu khin MODEM.
Bit
Chc nng
7
=1 : DCD ang hot ng, bo lin lc vi MODEM c thit lp.
6
=1 : RI ang hot ng
5
=1 : MODEM (hay MVT u kia) gi tn hiu DSR (Data Set Ready) v my
tnh cho bit sn sng nhn d liu (qua chn 6 ca DB9 hay DB25)
4
=1 : MODEM (hay MVT u kia) gi tn hiu CTS (Clear To Send) v my tnh
cho bit sn sng nhn d liu (qua chn 8 ca DB9 hay chn 5 ca
DB25).
3
=1 : bit D7 va i trng thi
2
=1 : bit D6 va i trng thi
1
=1 : bit D5 va i trng thi
0
=1 : bit D4 va i trng thi
k) Thanh ghi nh nhp (Scratch Register), a ch 3FFh
(dnh cho CPU, t s dng nn khng nghin cu)
51
D0 D7
Reset
MR
DISTR
DOSTR
MEMR I/O R
MEMW I/O W
8250
VXL
A0
A1
A0
A1
A2
A2
A3 A15
Gii
m a
ch
5V
0V
CS 2
CS1
CS0
SOUT
SIN
RTS
DTR
DSR
DCD
CTS
RI
RxD
TxD
MO
RTS
DTR DEM
DSR
DCD
CTS
RI
OUT1
OUT 2
XTAL1
CS
XTAL2
CS
ADS BAUDOUT
CS
DOSTR
RCKL
DISTR
52
53
54
55
IRQ
Common Uses
00
01
02
03
Exception Handlers
04
05 - 07
Exception Handlers
08
Hardware IRQ0
09
Hardware IRQ1
Bn phm
0A
Hardware IRQ2
Redirected
0B
Hardware IRQ3
0C
Hardware IRQ4
0D
Hardware IRQ5
Reserved/Sound Card
0E
Hardware IRQ6
iu khin a mm
0F
Hardware IRQ7
10 - 6F
70
Hardware IRQ8
71
Hardware IRQ9
Redirected IRQ2
72
Hardware IRQ10
Reserved
73
Hardware IRQ11
Reserved
74
Hardware IRQ12
PS/2 Mouse
75
Hardware IRQ13
Math's Co-Processor
76
Hardware IRQ14
77
Hardware IRQ15
Reserved
78 - FF
Software Interrupts
56
57
1
INTR
VXL INTA
BGN1
BGN2
BGN3
DI0DIn
INTA
INTA
(b)
(a)
Hnh 4.1: S u tin ngt theo v tr v vector ngt
Phng php ny tuy n gin nhng th t u tin khng thay i c v nu c
mt BGN no b hng, mch s lun bo c yu cu ngt.
u tin ngt dng mch so snh
Dng cc vi mch Intel 8214, 8259 c th thay i u tin ngt bng chng trnh.
4.2.3 Xc nh ngun gy ngt
C nhng phng php xc nh TBNV no gy ngt chuyn sang chng trnh
con phc v ngt tng ng cho TBNV :
-
58
K thut vo ra DMA (direct memory access) l phng php truy cp trc tip ti b
nh hoc I/O m khng c s tham gia ca CPU. Phng php ny trao i d liu gia
b nh v thit b ngoi vi vi tc cao v ch b hn ch bi tc ca b nh hoc
ca b iu khin DMA. Tc truyn DMA c th t ti 10 12 Kbyte/s vi cc b
nh RAM c tc cao. DMA c ng dng trong nhiu mc ch nhng thng thng
n c dng trong qu trnh "refresh" DRAM, xut mn hnh, c ghi a, truyn d
liu gia cc vng nh vi tc cao .
5.1.2 Hot ng DMAC (DMA Controller) c bn
Hai tn hiu yu cu v xc nhn trong h thng VXL l HOLD c s dng yu
cu DMA v HLDA l u ra xc nhn DMA. Khi tn hiu HOLD hot ng (HOLD =
1), DMA c yu cu. B VXL tr li bng cch kch hot tn hiu HLDA, xc nhn
yu cu, ng thi th ni cc cng vic hin thi cng cc bus d liu v a ch, iu
khin c t trng thi tr khng cao. Trng thi ny cho php cc thit b I/O bn
ngoi hoc cc b VXL khc nm quyn iu khin bus h thng truy cp trc tip b
nh . Tn hiu HOLD c mc u tin cao hn INTR hoc u vo NMI (ngt khng che
c) v ch sau RESET. Tn hiu HOLD lun c hiu lc ti bt k thi im no trong
sut qu trnh thc hin cc lnh khc ca VXL. Ch rng t lc tn hiu HOLD thay
i cho n khi tn hiu HLDA thay i tri qua mt s chu k clock .
DMA thng c thc hin gia thit b I/O v b nh. Qu trnh c DMA l qu trnh
a d liu t b nh ra thit b I/O, v ngc li qu trnh ghi DMA l qu trnh a d
liu t I/O ti b nh. Trong c hai chu trnh ny thit b I/O v b nh c iu khin
ng thi dn n cn c cc tn hiu iu khin khc nhau. iu khin qu trnh c
DMA ta cn hai tn hiu hot ng MEMR (c b nh ) v IOW (ghi I/O). iu
khin qu trnh ghi ta c hai tn hiu MEMW (ghi b b nh) v IOR (c I/O). B iu
khin DMA cung cp a ch b nh v tn hiu chn thit b I/O cho 8088 trong sut qu
trnh DMA. Do tc truyn DMA ph thuc vo tc ca b nh v tc ca b
iu khin DMA nn trong trng hp tc ca b iu khin DMA nh hn so vi b
nh th b iu khin DMA s lm gim tc chung ca h thng .
Hnh v sau minh ho qu trnh hot ng DMA c bn cng th thi gian c / ghi
DMA :
59
60
61
62
63
64
65
- Thanh ghi che set/reset (Mask register set/reset mode): xo ,thit lp vic cm cc knh
.
66
- Thanh ghi trng thi (Status register -SR ): xc nh trng thi ca cc knh DMA .
A2
A1
A0
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
1
1
1
1
1
0
0
0
1
1
0
0
0
1
1
0
0
1
0
1
0
1
1
0
1
IOR
0
1
1
1
1
1
0
1
1
1
IOW
1
0
0
0
0
0
1
0
0
0
Hot ng
c thanh ghi trng thi
Ghi thanh ghi lnh
Ghi thanh ghi yu cu
Ghi thanh ghi mt n n
Ghi thanh ghi ch
Xo flip-flop con tr byte
c thanh ghi tm thi
Xo ch
Xo thanh ghi mt n
Ghi tt c cc bit ca thanh ghi mt n
67
Thanh ghi
a ch c s
v hin hnh
a ch hin
hnh
m li c s
v hin hnh
m li hin
hnh
a ch c s
v hin hnh
a ch hin
hnh
m li c s
v hin hnh
m li hin
hnh
a ch c s
v hin hnh
a ch hin
hnh
m li c s
v hin hnh
m li hin
hnh
a ch c s
v hin hnh
a ch hin
hnh
m li c s
v hin hnh
m li hin
hnh
Hot
ng
Ghi
c
Ghi
c
Ghi
c
Ghi
c
Ghi
c
Ghi
c
Ghi
c
Ghi
c
CS
IOR
IOW A3
A2
A1
A0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Int
FF
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Data
Bus
A7A0
A8A15
A7A0
A8A15
W7W0
W15W8
W7W0
W15W8
A7A0
A8A15
A7A0
A8A15
W7W0
W15W8
W7W0
W15W8
A7A0
A8A15
A7A0
A8A15
W7W0
W15W8
W7W0
W15W8
A7A0
A8A15
A7A0
A8A15
W7W0
W15W8
W7W0
W15W8
68
69
70
71
port[addr_pFF]=$00;// xo con tr FF v 0.
// t a ch ngun vo knh 0
port[addr_chanel0] =$00;
port[addr_chanel0] =$10;
// t a ch ch vo knh 1
port[addr_pFF]=$01;// xo con tr FF v 0.
port[addr_chanel1] =$00;
port[addr_chanel1] =$14;
//Ch nh s byte cn chuyn 4000
port[addr_pFF]=$01;// xo con tr FF v 0.
port[addr_CT1] =$00;
port[addr_CT1] =$40;
// t ch : knh 0 c 1011 1000b= B8h ; knh 1 ghi: 1011 0101=B5h
port[addr_pFF]=$01;// xo con tr FF v 0.
port[addr_MR]=$B8;
port[addr_MR]=$B5;
// Lp trnh thanh ghi lnh cho php truyn M-M= 01h
Port[addr_CR]=$01;
// B mt n che chn knh 0 = 0000 1110 b=0Eh
port[addr_MKR]= $0E;
//Yu cu DMAC = 0000 0100 b=04h
port[addr_RR] = $04;
//Kim tra trng thi kt thc m: knh 0 truyn ht d liu (D0=1) =01h
Repeat
Var1=port[addr_SR];
Until ((var1 and $01)=$01);
//kt thc truyn
Return;
Sau khi khi ng, h thng DMAC s t hot ng m khng cn thm chng trnh
ph no na.
72
Setpoint
K
My vi tnh
DAC
ADC
CCCH
CB
73
Ud hiu in p vo
UP , IP in p vo v dng in vo ca thun.
UN , IN in p vo v dng in vo ca o.
Ur , Ir in p ra v dng in ra.
1. H s khuch i hiu K0
Khi khng ti c xc nh theo biu thc sau
K0 =
Ur
Ur
=
Ud U p U N
U r
U CM
74
K0
K CM
4. Dng vo tnh
I p + IN
2
vi UP = UN = 0
Dng vo lch khng l hiu cc dng vo tnh hai ca ca b khuch i thut ton
I0 = IP - IN vi UP = UN = 0
Thng thng I0 = 0,1IP. Tr s ca dng vo lch khng thay i theo nhit . Hin
tng ny gi l hin tng tri dng lch khng.
6.1.2 Cc s c bn ca b khuch i thut ton
1. S khuch i khng o
1
1
R2
1
1
K 0 R1 + R2 CMRR
75
R1 + R2
R2
2. Mch m
y l trng hp c bit ca mch khuch i khng o
R2
R1
76
77
4
2,5.10 12,5.103
10 5.10
V nguyn tc b chuyn i s-tng t tip nhn mt m s n bt song song hoc ni
tip li vo v bin i ra dng in hoc in p tng ng li ra. Dng in hay
in p li ra l hm bin thin ph hp theo m s li vo.
78
79
U ch
R i
2
Rf
(2
R
n 1
.Bn 1 + L + 20.B0
80
Rf
(2
2 .R
n
n 1
.Bn 1 + L + 20.B0
81
Gii m
WR
D0
D1
DAC
8 bit
D7
Bus MVT
BGN
Hnh 6.11: Mch ghp ni h VXL vi mt DAC 8 bits
a ch
A0A15
Gii m
WR
(3)
D0
74
273
D7
74
273
(1)
74
273
Bus MVT
BGN
DAC
16
bit
(2)
82
M ho
83
84
85
86
87
B N1
ADC
song song
DAC
N1 bit
TNG TH NHT
TNG
TH
HAI
Mach
hiu
Nhn
N1
2
Hnh 6.18: B chuyn i AD theo phng php song song ni tip kt hp.
y l s kt hp phng php song song v phng php ni tip nhm dung
ha u khuyt im ca hai phng php ny: gim bt phc tp ca phng php
song song v tng tc chuyn i so vi phng php ni tip.
Cng c th gi y l phng php phn on tng nhm bit, vi s bit trong
mi nhm N 2.
5. Chuyn i AD theo phng php tch phn hai sn dc
88
K
1
Ngun dao
ng
2
CNG
Uch
UA
Mach
logic
Flip Flop
tran
B m
Kt qua
Hnh 6.19: B chuyn i AD theo phng php tch phn hai sn dc.
VC
dc do
Uch tao ra
t1
t2
Z0
VSS
t
Hnh 6.20: th biu din nguyn l hot ng ca mch.
89
trng thi u tin, kha K lun t v tr 1. Mch tch phn s tch phn VA,
trong khi b m s m xung t ngun dao ng chun tn s fn. VA c tch phn
trong thi gian t1 cho n khi b m b trn (thi im t1). Lc ny mch logic s iu
khin chuyn kha K sang v tr 2 v mch tch phn s tip tc tch phn Vch nhng vi
chiu ngc li v Vch c cc tnh ngc cc tnh VA. Khi tn hiu ra ca b tch phn VC
gim xung bng 0 th mch so snh s ng cng. Ni dung ghi trong b m l kt qu
bin i. N t l vi thi gian tch phn in p chun t2.
Vin
D7
74
244
D7
D0
ADC
8 bit
D0
Finish
1
IOW
IOR
74
138
Cl
7474
D Q
A0
An
74125
Start
7404
GN
Bus
MVT
90
Port[addr_St]:=0;
Repeat
Var1 := port[addr_Fh];
Until ((Var1 AND 1)=1)
//Delay(thoigianchuyendoi) -> khong dung mach doc finish
Data :=port[addr_ADC];
91
7.1:
Hnh 7.1 v 7.2 cho thy MVT c ra sn mt s cc cng cho php ghp ni vi cc thit
b vo ra c bn (nh mn hnh, bn phm, chut, my in) v cc cng vo ra khc
(nh cng USP, khe cm m rng ISA/PCI slots) . Do mt vn t ra l phi thit
k cc mch ghp ni gia TBNV vi cc cng ny, phc v cho vic o lng v iu
khin mt h thng t ng ha.
92
7.2:
Ch rng VXL ch c mt bus d liu, trong khi c rt nhiu thit b ngoi vi v nh
cng mun trao i d liu vi VXL qua bus ny. Do mi thit b ngoi vi s c
cp mt a ch ring bit, cho php n lm vic vi VXL khi a ch ring bit c
a ra trn bus a ch. Bng 7.1 trnh by cc a ch vo ra c bn cho cc thit b ngoi
vi trong my vi tnh IPM.
Bng 7.1: a ch vo/ra c bn cho cc thit b trong cc my vi tnh IPM PC
Base Address
Device
0F - 1F
20 - 3F
40 - 5F
8254-2
60 - 6F
8042, Keyboard
93
70 - 7F
80 - 9F
87
DMA Channel 0
83
DMA Channel 1
81
DMA Channel 2
82
DMA Channel 3
8B
DMA Channel 5
89
DMA Channel 6
8A
DMA Channel 7
8F
Refresh
A0 - BF
C0 - DF
F0
F1
Reset 80287
F8 - FF
170-177
1F0 - 1F7
200 - 20F
Game Controller/Joystick
210 - 217
Expansion Unit
278 - 27F
94
280 - 29F
2E8 2EF
COM4
2E1
GPIB Adapter 0
2F8 - 2FF
COM2
2E2 2E3
Data acquisition
300 - 31F
Prototype Card
300 - 31F
320 - 32F
378 - 37F
380 38C
3A0 3A9
3B0 3BB
Monochrome display
3C0 3CF
3D0 3DF
3E8 3EF
COM3
3F0 3F7
3F8 3FF
COM1
95
96
97
2. u ni v cp:
2
DTrng
3
D+
Xanh lc
4
GND
en
Bng u ni bus USB
M t
+5VDC
D liuD liu+
NI t
1ms
667ns
83,3ns
98
0 1
1 0
Tn hiu NRZI
D+
Song
song/
nI
D-
B truyn USB
NRZI/
NI tip
song
song
B nhn USB
99
II. Cc HUB
u ni nhiu thit b ngoi vi USB ta cn 1 hub hoc nhiu hub. Hub l hp
phn phi bus c nhiu cng.
Mt hus ngoi c mt cng hng v my ch v 4 cng ra thit b ghp ni
,ngay trong my tnh PC cng c mt hub .Mt loi hub trong to ra 2 cng USB kiu
A pha sau may vi tnh.Hub ny gi l hub gc v hub ny t ngay trn mch chnh.(
hnh 5)
Cng USB
Trn PC
Hub USB
Tang 1
Nt
Tang 2
Nt
Nt
Tang 3
Nt
Tang 4
Nt
Nt
Nt
100
101
102
103
104
105
PHN II:
NG C BC.
I. c im chung v ng c bc
ng c bc thc cht l ng c ng b hot ng di tc dng ca cc
xung ri rc v k tip nhau. Khi mt xung dng in hoc in p t vo cun dy
phn ng ca ng c bc, th roto (phn cm) ca ng c s quay i mt gc nht
nh, v c gi l bc ca ng c, khi cc xung dng in t vo cun dy phn
ng lin tc th roto s quay lin tc.
V tr ca trc ng c bc c xc bng s lng xung, v vn tc ca ng c
t l vi tn s xung, v c xc nh bng s bc/giy (second). Tnh nng lm vic
ca ng c bc c t trng bi bc c thc hin, t tnh gc (quan h ca
mmen in t theo gc gia trc ca Roto v trc ca t trng tng), tn s xung gii
hn sao cho cc qu trnh qu , khi hon thnh mt bc c th tt i trc khi bt u
bc tip theo. Tnh nng m my ca ng c, c t trng bi tn s xung cc i
c th m my m khng lm cho Roto mt ng b (b bc). Tu theo kt cu ca
tng loi ng c, m tn s ng c c th tip nhn c t 10 n 10.000 Khz.
Bc ca ng c (gi tr ca gc gia hai v tr n nh k nhau ca Roto) cng
nh th chnh xc trong iu khin cng cao. Bc ca ng c ph thuc vo s cun
dy phn ng, s cc ca Stato, s rng ca Roto v phng php iu khin bc
hoc iu khin na bc. Ty theo yu cu v chnh xc v kt cu ca ng c, m
bc ca ng c thay i trong gii hn t 1800 - 0,180. Trong : ng c bc nam
chm vnh cu dng cc mng v c t tr thay i t 60 - 450, ng c bc c t tr
thay i c gc bc nm trong gii hn t: 1,80- 300, v ng c bc hn hp c gc
bc thay i trong khong 0,360 - 150. Cc gi tr gc ca cc loi ng c k trn c
tnh trong ch iu khin bc .
Chiu quay ca ng c bc khng ph thuc vo chiu dng in chy trong
cc cun dy phn ng, m ph thuc vo th t cun dy phn ng c cp xung iu
khin. Nhim v ny do b chuyn pht thc hin.
S cun dy phn ng (hay c gi l cun dy pha) ca ng c bc c ch
to t 2 - 5 cun dy pha (hay cn gi l bi dy) v c t i din nhau trong cc
rnh Stato. i vi cun dy phi c hai cun dy th ch dng cho iu khin lng
cc (cun dy c cc tnh thay i), vi 4 cun dy c th dng cho c hai ch iu
khin lng cc v iu khin n cc
ng c bc l mt thit b c s dng rng ri dng chuyn cc xung in
thnh chuyn ng c hc. mt s ng dng, chng hn nh b iu khin a, my in
kim ma trn v robot, th ng c bc c dng iu khin chuyn ng.
106
-6
107
1
2
S ng c bc hn hp.
ng c gm hai na Roto (1) v (2). Na(1) c nhiu rng trn Roto, na (2) l
nam chm vnh cu. Do c s kt hp gia hai phn nn to ra s kch thch roto
mnh hn. ng c loi ny c s bc t n 400 bc, nhng gi thnh t.
108
A
B
COM
C
D
COM
109
S bc/vng
500
200
180
144
72
48
24
110
Bc
1
2
3
4
Cun dy
A
1
0
0
0
Cun dy
B
0
1
0
0
Cun dy
C
0
0
1
0
Cun dy
D
0
0
0
1
Chiu quay
b m
111
112
113
Chn
7
Tn hiu
USBDP
Loi
I/O
8
6
27
USBDM
3.3VOUT
XTIN
I/O
OUT
IN
28
31
XTOUT
RCCLK
OUT
I/O
4
32
1
2
5
RESET
EECS
EESK
EEDATA
TEST
IN
I/O
I/O
I/O
IN
25
24
23
22
21
20
19
18
D0
D1
D2
D3
D4
D5
D6
D7
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Chc nng
Tn hiu d liu USB ph thuc vo tr 1.5k
gim in p ng ra cn 3.3V
Kt ni chn d liu m ca USB
Chn to in p 3.3V ti ng ra
Ly tn hiu t dao ng 6Mhz t dao ng thnh
anh
a tn hiu 6Mhz ra chn dao ng thch anh
RC-Timer m bo xung clock trn mode Sleep
v tc ng mc Low trong sut qua trnh chn
mode Reset hay Sleep
Reset ton b thit b s dng network RC ngoi
Ty chn EEPROM-chip chn
Ty chn EEPROM-xung ng h
Ty chn EEPROM-I/O d liu
t thit b vo mode Text- thit b phi c ni
t.
Bus d liu truyn trc tip Bit0
Bus d liu truyn trc tip Bit1
Bus d liu truyn trc tip Bit2
Bus d liu truyn trc tip Bit3
Bus d liu truyn trc tip Bit4
Bus d liu truyn trc tip Bit5
Bus d liu truyn trc tip Bit6
Bus d liu truyn trc tip Bit7
114
RD#
IN
15
WR
IN
14
TXE#
OUT
12
RXF#
OUT
11
EEREQ#
IN
10
EEGN#
OUT
3,13,26 VCC
9,17
GND
30
AVCC
PWR
PWR
PWR
115
116
25 chn
8
3
2
20
7
6
4
5
22
Chc nng
DCD _ Data Carrier Detect (Li
vo)
RxD _ Receive Data (Li vo)
TxD _ Transmit Data (Li ra)
DTR _ Data Terminal Ready (Li
ra)
GND _ Ground (Ni t)
DSR _ Data Set Ready (Li vo)
RTS _ Request to Send (Li ra)
CTS _ Clear to Send (Li vo)
RI _ Ring Indicator (Li ra)
117
RS_232
15m
(50FT)
RS_422
RS_423
RS_485
1.2km(4000FT 1.2km(4000FT 1.2km(4000FT
)
)
)
20Kps/15m 10Mbps/12m
10Mbps/120m
100Kbps/1.2k
m
100Kbs/9m
10Kbps/90m
1Kbps/1.2km
10Mbps/12m
1Mbps/120m
100Kbps/1.2k
m
118
Mode
Unbalanced
Driver No
Receiver
No
Logic 0
1
1
Logic 1
Community
(truyn
thng)
Cable/Signa
l
(Cp / tn
hiu)
Methode
(Phng
thc)
Balanced
Differental
1
10
Unbalnced
Differental
1
10
Balanced
Differental
32
32
+5V +15
V
-5V -15V
+2v +5V
+3.6V +6V
+1.5V +5V
-2V -5V
-3.6V -6V
-1.5V -5V
2V
1.8V
3.4V
1.3V
Simplex
Half_duplex
Full_duplex
Simplex
Half_duplex
Full_duplex
Simplex
Half_duplex
Full_duplex
150mA
150mA
150mA
Simplex
Half_duple
x
Full_duplex
Short circuit
500mA
current
119
Stop bit
+12V
-12V
D0
1
D1
1
D2
0
D3
1
D4
0
D5
0
D6
1
D7
0
T= 1/fbaud
1.04 ms
120
1
1.1RC
121
Ngt INTR
Ngt hay cn gi l kt thc vic chuyn i. y l chn ra tch cc mc thp.
Bnh thng chn ny trng thi cao v khi vic chuyn i hon tt th n
xung thp bo cho CPU bit l d liu c chuyn i sn sng ly i.
Sau khi INTR xung thp, cn t CS=0 v gi mt xung cao xung thp ti chn
RD a d liu ra.
Vin (+) v Vin(-)
y la hai u vo tng t vi sai, Trong Vin = Vin (+) - Vin (-)
Vin (-) c ni xung thp
122
Vcc
L chn ngun nui.
Vref/2
Chn 9 l in p u voc dng l in p tham chiu.
D0- D7
D0-D7 l cc chn ra d liu Cc chn nay c m ba trang thi v d liu
c chuyn i ch c truy cp khi chn CS = 0 v chn RD a xung mc
thp.
Dout=
Vin
kichthuocbuoc
Tr khng ca cm bin (K )
29.49
10
3.893
1.7
0.817
Di nhit
-550C ti +1500C
chnh xc
+ 10C
u ra
10mV/F
123
LM35
-550C ti +1500C
+ 1,50C
LM35CA
-400C ti +1100C
+ 10C
LM35C
-400C ti +1100C
+ 1,50C
LM35D
00C ti +1000C
+ 120C
Thng s k thut chnh ca cm bin nhit hLM35.
10mV/F
10mV/F
10mV/F
10mV/F
S0 S2 :
I0 I7 :
E
:
Z
:
Z
:
:
Vcc
GND :
Chn u vo
Ng vo a chc nng
Chn vo tc ng ( tc ng mc thp)
Ng ra a chc nng
Ng ra b sung a chc nng
Chn ngun
Chn ni t
124
125
126
II.
Nguyn l hot ng ca mch:
Mch o nh sng v iu khin n thng qua cng ni tip RS-232. Mch
s dng quang tr o nh sng iu khin n, vi in p chun 2.5V ly t
Diod Zener REF25Z, sau qua mch khuch i a LM358 a vo in p
chun 2.5V vo AD0804. AD0804 chuyn i tn hiu tng t t quang tr thnh
tn hiu s t D0 D7.
u vo quang tr dng tr 330 gim dng vo, 2 diod 4148 to ra
ngng dn.
Khi chn WR c kch mc logic 0 t chn RTS ca cng ni tip RS-232
th AD0804 bt u lm vic. Sau khi kt thc 8 chu k INTR bo kt thc. Tn
hiu tng t khi qua con AD0804 chuyn thnh tn hiu s, thng qua o 7414
a bit 1 vo chn LE (chip m) v OE ni mass s cho thng d liu. u ra
kch con ba trng thi thng d liu t 8 u vo D0 D7 khi u ra bng u
vo, mch cn li chuyn tn hiu truyn t song song qua ni tip.
Thng qua mch dao ng (7414, 10K, 10nF ) s to xung a vo IC74161
m t 000 111, sau quay tr li v c m mi nh vy.
QD c kch mc logic 0 s kch m 74151(A), sau 8 ln m c ln lt
a d liu ra u ra Y n chn RxD ca cng RS-232 thng qua my tnh iu
khin, in p s c a ra chn DTR +12V, dng qua Diod 20mA lm Diod
sng ln kch m Tranzitor, m C828 v H106. Lc ny Role in t ng ni
ngun AC n sng ln.
QAQBQC ln lt tc ng nh bng trng thi sau:
QA QB QC Y
0
0
0
D0
1
0
0
D1
0
1
0
D2
0
0
1
D3
Khi kt thc 111 chuyn qua 011 D7 tt. Qua u o iu khin tng t
74151(B) c c bit d liu D4 D7. Sau bit stop qua 3 bit Break. Vy cui cung
thu c 8 bit data,0 parity, 1 stop, 9600 Baud, 6 bit Break.
127
III.
Lu thut ton:
Khi pht ch
To tn hiu Start
Tt n DTR= -12
n DTR=12
128