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Keying
ECE 513 - Digital and Data
Communications 1
Prepared by: Engr. Jan Ray C. Rulida
Logic 1 = +1 V
Logic 0 = -1 V Balanced
Q channel fb/2 modulator ±cos ωct
Quaternary Phase-Shift Keying
Two bits ( a dibit) are clocked into the bit
splitter.
After both bits have been serially inputted,
they are simultaneously parallel outputted.
One bit is directed to the I channel and the
other is directed to the Q channel.
Quaternary Phase-Shift Keying
The I bit modulates a carrier that is in phase
with the reference oscillator (hence the name
“I” for “in phase channel).
The Q bit modulates a carrier that is 90° out of
phase or in quadrature with the reference
oscillator (hence the name “I” for “quadrature”
channel).
Quaternary Phase-Shift Keying
For a logic 1 = +1V and a logic 0 = -1V, two phases
are possible at the output of the I balanced
modulator (+sin ωct and -sin ωct) and two phases are
possible at the output of the Q balanced
modulator (+cos ωct and -cos ωct)
• •
10 11 10 11
sin(
ct)
sin(
ct)
sin(
ct)
sin(
ct)
00
01 00
• • 01
cos(
ct)
cos(
ct)
Quaternary Phase-Shift Keying
QPSK truth table
Binary Input Output Phase
Q I
0 0 -135°
0 1 -45°
1 0 135°
1 1 45°
Quaternary Phase-Shift Keying
QPSK Bandwidth Considerations (fN)
fb fb
fN 2
4 2
where: fN = double-sided Nyquist bandwidth
fb = input bit rate
M-ary Encoding (for M=4)
N = log2 M
N = 2 (for M = 4)
where: N = number of input bits
M = number of output conditions possible
with N bits